ulp_wdog.c 2.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/imx-regs.h>
  9. /*
  10. * MX7ULP WDOG Register Map
  11. */
  12. struct wdog_regs {
  13. u8 cs1;
  14. u8 cs2;
  15. u16 reserve0;
  16. u32 cnt;
  17. u32 toval;
  18. u32 win;
  19. };
  20. #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
  21. #define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
  22. #endif
  23. #define REFRESH_WORD0 0xA602 /* 1st refresh word */
  24. #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
  25. #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
  26. #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
  27. #define WDGCS1_WDGE (1<<7)
  28. #define WDGCS1_WDGUPDATE (1<<5)
  29. #define WDGCS2_FLG (1<<6)
  30. #define WDG_BUS_CLK (0x0)
  31. #define WDG_LPO_CLK (0x1)
  32. #define WDG_32KHZ_CLK (0x2)
  33. #define WDG_EXT_CLK (0x3)
  34. void hw_watchdog_set_timeout(u16 val)
  35. {
  36. /* setting timeout value */
  37. struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
  38. writel(val, &wdog->toval);
  39. }
  40. void hw_watchdog_reset(void)
  41. {
  42. struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
  43. writel(REFRESH_WORD0, &wdog->cnt);
  44. writel(REFRESH_WORD1, &wdog->cnt);
  45. }
  46. void hw_watchdog_init(void)
  47. {
  48. u8 val;
  49. struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
  50. writel(UNLOCK_WORD0, &wdog->cnt);
  51. writel(UNLOCK_WORD1, &wdog->cnt);
  52. val = readb(&wdog->cs2);
  53. val |= WDGCS2_FLG;
  54. writeb(val, &wdog->cs2);
  55. hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
  56. writel(0, &wdog->win);
  57. writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
  58. writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */
  59. hw_watchdog_reset();
  60. }
  61. void reset_cpu(ulong addr)
  62. {
  63. struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
  64. writel(UNLOCK_WORD0, &wdog->cnt);
  65. writel(UNLOCK_WORD1, &wdog->cnt);
  66. hw_watchdog_set_timeout(5); /* 5ms timeout */
  67. writel(0, &wdog->win);
  68. writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
  69. writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */
  70. hw_watchdog_reset();
  71. while (1);
  72. }