designware_wdt.c 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <watchdog.h>
  7. #include <asm/io.h>
  8. #include <asm/utils.h>
  9. #define DW_WDT_CR 0x00
  10. #define DW_WDT_TORR 0x04
  11. #define DW_WDT_CRR 0x0C
  12. #define DW_WDT_CR_EN_OFFSET 0x00
  13. #define DW_WDT_CR_RMOD_OFFSET 0x01
  14. #define DW_WDT_CR_RMOD_VAL 0x00
  15. #define DW_WDT_CRR_RESTART_VAL 0x76
  16. /*
  17. * Set the watchdog time interval.
  18. * Counter is 32 bit.
  19. */
  20. static int designware_wdt_settimeout(unsigned int timeout)
  21. {
  22. signed int i;
  23. /* calculate the timeout range value */
  24. i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ)) - 16;
  25. if (i > 15)
  26. i = 15;
  27. if (i < 0)
  28. i = 0;
  29. writel((i | (i << 4)), (CONFIG_DW_WDT_BASE + DW_WDT_TORR));
  30. return 0;
  31. }
  32. static void designware_wdt_enable(void)
  33. {
  34. writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
  35. (0x1 << DW_WDT_CR_EN_OFFSET)),
  36. (CONFIG_DW_WDT_BASE + DW_WDT_CR));
  37. }
  38. static unsigned int designware_wdt_is_enabled(void)
  39. {
  40. unsigned long val;
  41. val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR));
  42. return val & 0x1;
  43. }
  44. #if defined(CONFIG_HW_WATCHDOG)
  45. void hw_watchdog_reset(void)
  46. {
  47. if (designware_wdt_is_enabled())
  48. /* restart the watchdog counter */
  49. writel(DW_WDT_CRR_RESTART_VAL,
  50. (CONFIG_DW_WDT_BASE + DW_WDT_CRR));
  51. }
  52. void hw_watchdog_init(void)
  53. {
  54. /* reset to disable the watchdog */
  55. hw_watchdog_reset();
  56. /* set timer in miliseconds */
  57. designware_wdt_settimeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
  58. /* enable the watchdog */
  59. designware_wdt_enable();
  60. /* reset the watchdog */
  61. hw_watchdog_reset();
  62. }
  63. #endif