board.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2018 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <fdtdec.h>
  9. #include <init.h>
  10. #include <malloc.h>
  11. #include <time.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <dm/device.h>
  16. #include <dm/uclass.h>
  17. #include <versalpl.h>
  18. #include <linux/sizes.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #if defined(CONFIG_FPGA_VERSALPL)
  21. static xilinx_desc versalpl = XILINX_VERSAL_DESC;
  22. #endif
  23. int board_init(void)
  24. {
  25. printf("EL Level:\tEL%d\n", current_el());
  26. #if defined(CONFIG_FPGA_VERSALPL)
  27. fpga_init();
  28. fpga_add(fpga_xilinx, &versalpl);
  29. #endif
  30. return 0;
  31. }
  32. int board_early_init_r(void)
  33. {
  34. u32 val;
  35. if (current_el() != 3)
  36. return 0;
  37. debug("iou_switch ctrl div0 %x\n",
  38. readl(&crlapb_base->iou_switch_ctrl));
  39. writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  40. (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  41. &crlapb_base->iou_switch_ctrl);
  42. /* Global timer init - Program time stamp reference clk */
  43. val = readl(&crlapb_base->timestamp_ref_ctrl);
  44. val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  45. writel(val, &crlapb_base->timestamp_ref_ctrl);
  46. debug("ref ctrl 0x%x\n",
  47. readl(&crlapb_base->timestamp_ref_ctrl));
  48. /* Clear reset of timestamp reg */
  49. writel(0, &crlapb_base->rst_timestamp);
  50. /*
  51. * Program freq register in System counter and
  52. * enable system counter.
  53. */
  54. writel(COUNTER_FREQUENCY,
  55. &iou_scntr_secure->base_frequency_id_register);
  56. debug("counter val 0x%x\n",
  57. readl(&iou_scntr_secure->base_frequency_id_register));
  58. writel(IOU_SCNTRS_CONTROL_EN,
  59. &iou_scntr_secure->counter_control_register);
  60. debug("scntrs control 0x%x\n",
  61. readl(&iou_scntr_secure->counter_control_register));
  62. debug("timer 0x%llx\n", get_ticks());
  63. debug("timer 0x%llx\n", get_ticks());
  64. return 0;
  65. }
  66. int board_late_init(void)
  67. {
  68. u32 reg = 0;
  69. u8 bootmode;
  70. struct udevice *dev;
  71. int bootseq = -1;
  72. int bootseq_len = 0;
  73. int env_targets_len = 0;
  74. const char *mode;
  75. char *new_targets;
  76. char *env_targets;
  77. ulong initrd_hi;
  78. if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  79. debug("Saved variables - Skipping\n");
  80. return 0;
  81. }
  82. reg = readl(&crp_base->boot_mode_usr);
  83. if (reg >> BOOT_MODE_ALT_SHIFT)
  84. reg >>= BOOT_MODE_ALT_SHIFT;
  85. bootmode = reg & BOOT_MODES_MASK;
  86. puts("Bootmode: ");
  87. switch (bootmode) {
  88. case USB_MODE:
  89. puts("USB_MODE\n");
  90. mode = "dfu_usb";
  91. break;
  92. case JTAG_MODE:
  93. puts("JTAG_MODE\n");
  94. mode = "jtag pxe dhcp";
  95. break;
  96. case QSPI_MODE_24BIT:
  97. puts("QSPI_MODE_24\n");
  98. mode = "xspi0";
  99. break;
  100. case QSPI_MODE_32BIT:
  101. puts("QSPI_MODE_32\n");
  102. mode = "xspi0";
  103. break;
  104. case OSPI_MODE:
  105. puts("OSPI_MODE\n");
  106. mode = "xspi0";
  107. break;
  108. case EMMC_MODE:
  109. puts("EMMC_MODE\n");
  110. if (uclass_get_device_by_name(UCLASS_MMC,
  111. "sdhci@f1050000", &dev)) {
  112. puts("Boot from EMMC but without SD1 enabled!\n");
  113. return -1;
  114. }
  115. debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
  116. mode = "mmc";
  117. bootseq = dev->seq;
  118. break;
  119. case SD_MODE:
  120. puts("SD_MODE\n");
  121. if (uclass_get_device_by_name(UCLASS_MMC,
  122. "sdhci@f1040000", &dev)) {
  123. puts("Boot from SD0 but without SD0 enabled!\n");
  124. return -1;
  125. }
  126. debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
  127. mode = "mmc";
  128. bootseq = dev->seq;
  129. break;
  130. case SD1_LSHFT_MODE:
  131. puts("LVL_SHFT_");
  132. /* fall through */
  133. case SD_MODE1:
  134. puts("SD_MODE1\n");
  135. if (uclass_get_device_by_name(UCLASS_MMC,
  136. "sdhci@f1050000", &dev)) {
  137. puts("Boot from SD1 but without SD1 enabled!\n");
  138. return -1;
  139. }
  140. debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
  141. mode = "mmc";
  142. bootseq = dev->seq;
  143. break;
  144. default:
  145. mode = "";
  146. printf("Invalid Boot Mode:0x%x\n", bootmode);
  147. break;
  148. }
  149. if (bootseq >= 0) {
  150. bootseq_len = snprintf(NULL, 0, "%i", bootseq);
  151. debug("Bootseq len: %x\n", bootseq_len);
  152. }
  153. /*
  154. * One terminating char + one byte for space between mode
  155. * and default boot_targets
  156. */
  157. env_targets = env_get("boot_targets");
  158. if (env_targets)
  159. env_targets_len = strlen(env_targets);
  160. new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
  161. bootseq_len);
  162. if (!new_targets)
  163. return -ENOMEM;
  164. if (bootseq >= 0)
  165. sprintf(new_targets, "%s%x %s", mode, bootseq,
  166. env_targets ? env_targets : "");
  167. else
  168. sprintf(new_targets, "%s %s", mode,
  169. env_targets ? env_targets : "");
  170. env_set("boot_targets", new_targets);
  171. initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
  172. initrd_hi = round_down(initrd_hi, SZ_16M);
  173. env_set_addr("initrd_high", (void *)initrd_hi);
  174. env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
  175. return 0;
  176. }
  177. int dram_init_banksize(void)
  178. {
  179. int ret;
  180. ret = fdtdec_setup_memory_banksize();
  181. if (ret)
  182. return ret;
  183. mem_map_fill();
  184. return 0;
  185. }
  186. int dram_init(void)
  187. {
  188. if (fdtdec_setup_mem_size_base() != 0)
  189. return -EINVAL;
  190. return 0;
  191. }
  192. void reset_cpu(ulong addr)
  193. {
  194. }