iot_devkit.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <malloc.h>
  8. #include <dwmmc.h>
  9. #include <linux/libfdt.h>
  10. #include <fdtdec.h>
  11. #include <asm/arcregs.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. #define SYSCON_BASE 0xf000a000
  14. #define AHBCKDIV (void *)(SYSCON_BASE + 0x04)
  15. #define APBCKDIV (void *)(SYSCON_BASE + 0x08)
  16. #define APBCKEN (void *)(SYSCON_BASE + 0x0C)
  17. #define RESET_REG (void *)(SYSCON_BASE + 0x18)
  18. #define CLKSEL (void *)(SYSCON_BASE + 0x24)
  19. #define CLKSTAT (void *)(SYSCON_BASE + 0x28)
  20. #define PLLCON (void *)(SYSCON_BASE + 0x2C)
  21. #define APBCKSEL (void *)(SYSCON_BASE + 0x30)
  22. #define AHBCKEN (void *)(SYSCON_BASE + 0x34)
  23. #define USBPHY_PLL (void *)(SYSCON_BASE + 0x78)
  24. #define USBCFG (void *)(SYSCON_BASE + 0x7c)
  25. #define PLL_MASK_0 0xffcfffff
  26. #define PLL_MASK_1 0xffcfff00
  27. #define PLL_MASK_2 0xfbcfff00
  28. #define CLKSEL_DEFAULT 0x5a690000
  29. static int set_cpu_freq(unsigned int clk)
  30. {
  31. clk /= 1000000;
  32. /* Set clk to ext Xtal (LSN value 0) */
  33. writel(CLKSEL_DEFAULT, CLKSEL);
  34. switch (clk) {
  35. case 16:
  36. /* Bypass mode */
  37. return 0;
  38. case 50:
  39. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  40. /* pll_off=1, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
  41. writel((readl(PLLCON) & PLL_MASK_1) | 0x300191, PLLCON);
  42. /* pll_off=0, M=25, N=1, OD=3, PLL_OUT_CLK=50M */
  43. writel((readl(PLLCON) & PLL_MASK_2) | 0x300191, PLLCON);
  44. break;
  45. case 72:
  46. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  47. /* pll_off=1, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
  48. writel((readl(PLLCON) & PLL_MASK_1) | 0x200121, PLLCON);
  49. /* pll_off=0, M=18, N=1, OD=2, PLL_OUT_CLK=72M */
  50. writel((readl(PLLCON) & PLL_MASK_2) | 0x200121, PLLCON);
  51. break;
  52. case 100:
  53. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  54. /* pll_off=1,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
  55. writel((readl(PLLCON) & PLL_MASK_1) | 0x200191, PLLCON);
  56. /* pll_off=0,M=25, N=1, OD=2, PLL_OUT_CLK=100M */
  57. writel((readl(PLLCON) & PLL_MASK_2) | 0x200191, PLLCON);
  58. break;
  59. case 136:
  60. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  61. /* pll_off=1, M=17, N=1, OD=1, PLL_OUT_CLK=136M */
  62. writel((readl(PLLCON) & PLL_MASK_1) | 0x100111, PLLCON);
  63. /* pll_off=0, M=17, N=1, OD=1, PLL_OUT_CLK=136M */
  64. writel((readl(PLLCON) & PLL_MASK_2) | 0x100111, PLLCON);
  65. break;
  66. case 144:
  67. writel(readl(PLLCON) & PLL_MASK_0, PLLCON);
  68. /* pll_off=1, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
  69. writel((readl(PLLCON) & PLL_MASK_1) | 0x100121, PLLCON);
  70. /* pll_off=0, M=18, N=1, OD=1, PLL_OUT_CLK=144M */
  71. writel((readl(PLLCON) & PLL_MASK_2) | 0x100121, PLLCON);
  72. break;
  73. default:
  74. return -EINVAL;
  75. }
  76. while (!(readl(CLKSTAT) & 0x4))
  77. ;
  78. /* Set clk from PLL on bus (LSN = 1) */
  79. writel(CLKSEL_DEFAULT | BIT(0), CLKSEL);
  80. return 0;
  81. }
  82. extern u8 __rom_end[];
  83. extern u8 __ram_start[];
  84. extern u8 __ram_end[];
  85. /*
  86. * Use mach_cpu_init() for .data section copy as board_early_init_f() will be
  87. * too late: initf_dm() will use a value of "av_" variable from not yet
  88. * initialized (by copy) area.
  89. */
  90. int mach_cpu_init(void)
  91. {
  92. int offset;
  93. /* Don't relocate U-Boot */
  94. gd->flags |= GD_FLG_SKIP_RELOC;
  95. /* Copy data from ROM to RAM */
  96. u8 *src = __rom_end;
  97. u8 *dst = __ram_start;
  98. while (dst < __ram_end)
  99. *dst++ = *src++;
  100. /* Enable debug uart */
  101. #define DEBUG_UART_BASE 0x80014000
  102. #define DEBUG_UART_DLF_OFFSET 0xc0
  103. write_aux_reg(DEBUG_UART_BASE + DEBUG_UART_DLF_OFFSET, 1);
  104. offset = fdt_path_offset(gd->fdt_blob, "/cpu_card/core_clk");
  105. if (offset < 0)
  106. return offset;
  107. gd->cpu_clk = fdtdec_get_int(gd->fdt_blob, offset, "clock-frequency", 0);
  108. if (!gd->cpu_clk)
  109. return -EINVAL;
  110. /* If CPU freq > 100 MHz, divide eFLASH clock by 2 */
  111. if (gd->cpu_clk > 100000000) {
  112. u32 reg = readl(AHBCKDIV);
  113. reg &= ~(0xF << 8);
  114. reg |= 2 << 8;
  115. writel(reg, AHBCKDIV);
  116. }
  117. return set_cpu_freq(gd->cpu_clk);
  118. }
  119. #define IOTDK_RESET_SEQ 0x55AA6699
  120. void reset_cpu(ulong addr)
  121. {
  122. writel(IOTDK_RESET_SEQ, RESET_REG);
  123. }
  124. int checkboard(void)
  125. {
  126. puts("Board: Synopsys IoT Development Kit\n");
  127. return 0;
  128. };