silk_spl.c 9.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * board/renesas/silk/silk_spl.c
  4. *
  5. * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <malloc.h>
  10. #include <dm/platform_data/serial_sh.h>
  11. #include <asm/processor.h>
  12. #include <asm/mach-types.h>
  13. #include <asm/io.h>
  14. #include <linux/errno.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/gpio.h>
  17. #include <asm/arch/rmobile.h>
  18. #include <asm/arch/rcar-mstp.h>
  19. #include <spl.h>
  20. #define TMU0_MSTP125 BIT(25)
  21. #define SCIF2_MSTP719 BIT(19)
  22. #define QSPI_MSTP917 BIT(17)
  23. #define SD1CKCR 0xE6150078
  24. #define SD_97500KHZ 0x7
  25. struct reg_config {
  26. u16 off;
  27. u32 val;
  28. };
  29. static void dbsc_wait(u16 reg)
  30. {
  31. static const u32 dbsc3_0_base = DBSC3_0_BASE;
  32. while (!(readl(dbsc3_0_base + reg) & BIT(0)))
  33. ;
  34. }
  35. static void spl_init_sys(void)
  36. {
  37. u32 r0 = 0;
  38. writel(0xa5a5a500, 0xe6020004);
  39. writel(0xa5a5a500, 0xe6030004);
  40. asm volatile(
  41. /* ICIALLU - Invalidate I$ to PoU */
  42. "mcr 15, 0, %0, cr7, cr5, 0 \n"
  43. /* BPIALL - Invalidate branch predictors */
  44. "mcr 15, 0, %0, cr7, cr5, 6 \n"
  45. /* Set SCTLR[IZ] */
  46. "mrc 15, 0, %0, cr1, cr0, 0 \n"
  47. "orr %0, #0x1800 \n"
  48. "mcr 15, 0, %0, cr1, cr0, 0 \n"
  49. "isb sy \n"
  50. :"=r"(r0));
  51. }
  52. static void spl_init_pfc(void)
  53. {
  54. static const struct reg_config pfc_with_unlock[] = {
  55. { 0x0090, 0x00018040 },
  56. { 0x0094, 0x00000000 },
  57. { 0x0098, 0x00000000 },
  58. { 0x0020, 0x94000000 },
  59. { 0x0024, 0x00000006 },
  60. { 0x0028, 0x40000000 },
  61. { 0x002c, 0x00000155 },
  62. { 0x0030, 0x00000002 },
  63. { 0x0034, 0x00000000 },
  64. { 0x0038, 0x00000000 },
  65. { 0x003c, 0x00000000 },
  66. { 0x0040, 0x60000000 },
  67. { 0x0044, 0x36dab6db },
  68. { 0x0048, 0x926da012 },
  69. { 0x004c, 0x0008c383 },
  70. { 0x0050, 0x00000000 },
  71. { 0x0054, 0x00000140 },
  72. { 0x0004, 0xffffffff },
  73. { 0x0008, 0x00ec3fff },
  74. { 0x000c, 0x5bffffff },
  75. { 0x0010, 0x01bfe1ff },
  76. { 0x0014, 0x5bffffff },
  77. { 0x0018, 0x0f4b200f },
  78. { 0x001c, 0x03ffffff },
  79. };
  80. static const struct reg_config pfc_without_unlock[] = {
  81. { 0x0100, 0x00000000 },
  82. { 0x0104, 0x4203fdf0 },
  83. { 0x0108, 0x00000000 },
  84. { 0x010c, 0x159007ff },
  85. { 0x0110, 0x80000000 },
  86. { 0x0114, 0x00de481f },
  87. { 0x0118, 0x00000000 },
  88. };
  89. static const struct reg_config pfc_with_unlock2[] = {
  90. { 0x0060, 0xffffffff },
  91. { 0x0064, 0xfffff000 },
  92. { 0x0068, 0x55555500 },
  93. { 0x006c, 0xffffff00 },
  94. { 0x0070, 0x00000000 },
  95. };
  96. static const u32 pfc_base = 0xe6060000;
  97. unsigned int i;
  98. for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
  99. writel(~pfc_with_unlock[i].val, pfc_base);
  100. writel(pfc_with_unlock[i].val,
  101. pfc_base | pfc_with_unlock[i].off);
  102. }
  103. for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
  104. writel(pfc_without_unlock[i].val,
  105. pfc_base | pfc_without_unlock[i].off);
  106. for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) {
  107. writel(~pfc_with_unlock2[i].val, pfc_base);
  108. writel(pfc_with_unlock2[i].val,
  109. pfc_base | pfc_with_unlock2[i].off);
  110. }
  111. }
  112. static void spl_init_gpio(void)
  113. {
  114. static const u16 gpio_offs[] = {
  115. 0x1000, 0x2000, 0x3000, 0x4000
  116. };
  117. static const struct reg_config gpio_set[] = {
  118. { 0x2000, 0x24000000 },
  119. { 0x4000, 0xa4000000 },
  120. { 0x5000, 0x0084c000 },
  121. };
  122. static const struct reg_config gpio_clr[] = {
  123. { 0x1000, 0x01000000 },
  124. { 0x2000, 0x24000000 },
  125. { 0x3000, 0x00000000 },
  126. { 0x4000, 0xa4000000 },
  127. { 0x5000, 0x00044380 },
  128. };
  129. static const u32 gpio_base = 0xe6050000;
  130. unsigned int i;
  131. for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
  132. writel(0, gpio_base | 0x20 | gpio_offs[i]);
  133. writel(BIT(23), gpio_base | 0x5020);
  134. for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
  135. writel(0, gpio_base | 0x00 | gpio_offs[i]);
  136. writel(BIT(23), gpio_base | 0x5000);
  137. for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
  138. writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
  139. for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
  140. writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
  141. }
  142. static void spl_init_lbsc(void)
  143. {
  144. static const struct reg_config lbsc_config[] = {
  145. { 0x00, 0x00000020 },
  146. { 0x08, 0x00002020 },
  147. { 0x30, 0x2a103320 },
  148. { 0x38, 0xff70ff70 },
  149. };
  150. static const u16 lbsc_offs[] = {
  151. 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8
  152. };
  153. static const u32 lbsc_base = 0xfec00200;
  154. unsigned int i;
  155. for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
  156. writel(lbsc_config[i].val,
  157. lbsc_base | lbsc_config[i].off);
  158. writel(lbsc_config[i].val,
  159. lbsc_base | (lbsc_config[i].off + 4));
  160. }
  161. for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
  162. writel(0, lbsc_base | lbsc_offs[i]);
  163. }
  164. static void spl_init_dbsc(void)
  165. {
  166. static const struct reg_config dbsc_config1[] = {
  167. { 0x0018, 0x21000000 },
  168. { 0x0018, 0x11000000 },
  169. { 0x0018, 0x10000000 },
  170. { 0x0280, 0x0000a55a },
  171. { 0x0290, 0x00000001 },
  172. { 0x02a0, 0x80000000 },
  173. { 0x0290, 0x00000004 },
  174. };
  175. static const struct reg_config dbsc_config2[] = {
  176. { 0x0290, 0x00000006 },
  177. { 0x02a0, 0x0005c000 },
  178. };
  179. static const struct reg_config dbsc_config3r2[] = {
  180. { 0x0290, 0x0000000f },
  181. { 0x02a0, 0x00181224 },
  182. };
  183. static const struct reg_config dbsc_config4[] = {
  184. { 0x0290, 0x00000010 },
  185. { 0x02a0, 0xf004649b },
  186. { 0x0290, 0x00000061 },
  187. { 0x02a0, 0x0000006d },
  188. { 0x0290, 0x00000001 },
  189. { 0x02a0, 0x00000073 },
  190. { 0x0020, 0x00000007 },
  191. { 0x0024, 0x0f030a02 },
  192. { 0x0030, 0x00000001 },
  193. { 0x00b0, 0x00000000 },
  194. { 0x0040, 0x00000009 },
  195. { 0x0044, 0x00000007 },
  196. { 0x0048, 0x00000000 },
  197. { 0x0050, 0x00000009 },
  198. { 0x0054, 0x000a0009 },
  199. { 0x0058, 0x00000021 },
  200. { 0x005c, 0x00000018 },
  201. { 0x0060, 0x00000005 },
  202. { 0x0064, 0x00000020 },
  203. { 0x0068, 0x00000007 },
  204. { 0x006c, 0x0000000a },
  205. { 0x0070, 0x00000009 },
  206. { 0x0074, 0x00000010 },
  207. { 0x0078, 0x000000ae },
  208. { 0x007c, 0x00140005 },
  209. { 0x0080, 0x00050004 },
  210. { 0x0084, 0x50213005 },
  211. { 0x0088, 0x000c0000 },
  212. { 0x008c, 0x00000200 },
  213. { 0x0090, 0x00000040 },
  214. { 0x0100, 0x00000001 },
  215. { 0x00c0, 0x00020001 },
  216. { 0x00c8, 0x20042004 },
  217. { 0x0380, 0x00020003 },
  218. { 0x0390, 0x0000001f },
  219. };
  220. static const struct reg_config dbsc_config5[] = {
  221. { 0x0244, 0x00000011 },
  222. { 0x0290, 0x00000003 },
  223. { 0x02a0, 0x0300c4e1 },
  224. { 0x0290, 0x00000023 },
  225. { 0x02a0, 0x00fcb6d0 },
  226. { 0x0290, 0x00000011 },
  227. { 0x02a0, 0x1000040b },
  228. { 0x0290, 0x00000012 },
  229. { 0x02a0, 0x85589955 },
  230. { 0x0290, 0x00000013 },
  231. { 0x02a0, 0x1a852400 },
  232. { 0x0290, 0x00000014 },
  233. { 0x02a0, 0x300210b4 },
  234. { 0x0290, 0x00000015 },
  235. { 0x02a0, 0x00000b50 },
  236. { 0x0290, 0x00000016 },
  237. { 0x02a0, 0x00000006 },
  238. { 0x0290, 0x00000017 },
  239. { 0x02a0, 0x00000010 },
  240. { 0x0290, 0x0000001a },
  241. { 0x02a0, 0x910035c7 },
  242. { 0x0290, 0x00000004 },
  243. };
  244. static const struct reg_config dbsc_config6[] = {
  245. { 0x0290, 0x00000001 },
  246. { 0x02a0, 0x00000181 },
  247. { 0x0018, 0x11000000 },
  248. { 0x0290, 0x00000004 },
  249. };
  250. static const struct reg_config dbsc_config7[] = {
  251. { 0x0290, 0x00000001 },
  252. { 0x02a0, 0x0000fe01 },
  253. { 0x0304, 0x00000000 },
  254. { 0x00f4, 0x01004c20 },
  255. { 0x00f8, 0x012c00be },
  256. { 0x00e0, 0x00000140 },
  257. { 0x00e4, 0x00081450 },
  258. { 0x00e8, 0x00010000 },
  259. { 0x0290, 0x00000004 },
  260. };
  261. static const struct reg_config dbsc_config8[] = {
  262. { 0x0014, 0x00000001 },
  263. { 0x0290, 0x00000010 },
  264. { 0x02a0, 0xf00464db },
  265. { 0x0010, 0x00000001 },
  266. { 0x0280, 0x00000000 },
  267. };
  268. static const u32 dbsc3_0_base = DBSC3_0_BASE;
  269. unsigned int i;
  270. for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++)
  271. writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
  272. dbsc_wait(0x2a0);
  273. for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++)
  274. writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
  275. for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
  276. writel(dbsc_config3r2[i].val,
  277. dbsc3_0_base | dbsc_config3r2[i].off);
  278. }
  279. for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++)
  280. writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
  281. dbsc_wait(0x240);
  282. for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++)
  283. writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
  284. dbsc_wait(0x2a0);
  285. for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++)
  286. writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
  287. dbsc_wait(0x2a0);
  288. for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++)
  289. writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
  290. dbsc_wait(0x2a0);
  291. for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++)
  292. writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
  293. }
  294. static void spl_init_qspi(void)
  295. {
  296. mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
  297. static const u32 qspi_base = 0xe6b10000;
  298. writeb(0x08, qspi_base + 0x00);
  299. writeb(0x00, qspi_base + 0x01);
  300. writeb(0x06, qspi_base + 0x02);
  301. writeb(0x01, qspi_base + 0x0a);
  302. writeb(0x00, qspi_base + 0x0b);
  303. writeb(0x00, qspi_base + 0x0c);
  304. writeb(0x00, qspi_base + 0x0d);
  305. writeb(0x00, qspi_base + 0x0e);
  306. writew(0xe080, qspi_base + 0x10);
  307. writeb(0xc0, qspi_base + 0x18);
  308. writeb(0x00, qspi_base + 0x18);
  309. writeb(0x00, qspi_base + 0x08);
  310. writeb(0x48, qspi_base + 0x00);
  311. }
  312. void board_init_f(ulong dummy)
  313. {
  314. mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  315. mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
  316. /* Set SD1 to the 97.5MHz */
  317. writel(SD_97500KHZ, SD1CKCR);
  318. spl_init_sys();
  319. spl_init_pfc();
  320. spl_init_gpio();
  321. spl_init_lbsc();
  322. spl_init_dbsc();
  323. spl_init_qspi();
  324. }
  325. void spl_board_init(void)
  326. {
  327. /* UART clocks enabled and gd valid - init serial console */
  328. preloader_console_init();
  329. }
  330. void board_boot_order(u32 *spl_boot_list)
  331. {
  332. const u32 jtag_magic = 0x1337c0de;
  333. const u32 load_magic = 0xb33fc0de;
  334. /*
  335. * If JTAG probe sets special word at 0xe6300020, then it must
  336. * put U-Boot into RAM and SPL will start it from RAM.
  337. */
  338. if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
  339. printf("JTAG boot detected!\n");
  340. while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
  341. ;
  342. spl_boot_list[0] = BOOT_DEVICE_RAM;
  343. spl_boot_list[1] = BOOT_DEVICE_NONE;
  344. return;
  345. }
  346. /* Boot from SPI NOR with YMODEM UART fallback. */
  347. spl_boot_list[0] = BOOT_DEVICE_SPI;
  348. spl_boot_list[1] = BOOT_DEVICE_UART;
  349. spl_boot_list[2] = BOOT_DEVICE_NONE;
  350. }
  351. void reset_cpu(ulong addr)
  352. {
  353. }