koelsch_spl.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * board/renesas/koelsch/koelsch_spl.c
  4. *
  5. * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <malloc.h>
  10. #include <dm/platform_data/serial_sh.h>
  11. #include <asm/processor.h>
  12. #include <asm/mach-types.h>
  13. #include <asm/io.h>
  14. #include <linux/errno.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/gpio.h>
  17. #include <asm/arch/rmobile.h>
  18. #include <asm/arch/rcar-mstp.h>
  19. #include <spl.h>
  20. #define TMU0_MSTP125 BIT(25)
  21. #define SCIF0_MSTP721 BIT(21)
  22. #define QSPI_MSTP917 BIT(17)
  23. #define SD2CKCR 0xE615026C
  24. #define SD_97500KHZ 0x7
  25. struct reg_config {
  26. u16 off;
  27. u32 val;
  28. };
  29. static void dbsc_wait(u16 reg)
  30. {
  31. static const u32 dbsc3_0_base = DBSC3_0_BASE;
  32. static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
  33. while (!(readl(dbsc3_0_base + reg) & BIT(0)))
  34. ;
  35. while (!(readl(dbsc3_1_base + reg) & BIT(0)))
  36. ;
  37. }
  38. static void spl_init_sys(void)
  39. {
  40. u32 r0 = 0;
  41. writel(0xa5a5a500, 0xe6020004);
  42. writel(0xa5a5a500, 0xe6030004);
  43. asm volatile(
  44. /* ICIALLU - Invalidate I$ to PoU */
  45. "mcr 15, 0, %0, cr7, cr5, 0 \n"
  46. /* BPIALL - Invalidate branch predictors */
  47. "mcr 15, 0, %0, cr7, cr5, 6 \n"
  48. /* Set SCTLR[IZ] */
  49. "mrc 15, 0, %0, cr1, cr0, 0 \n"
  50. "orr %0, #0x1800 \n"
  51. "mcr 15, 0, %0, cr1, cr0, 0 \n"
  52. "isb sy \n"
  53. :"=r"(r0));
  54. }
  55. static void spl_init_pfc(void)
  56. {
  57. static const struct reg_config pfc_with_unlock[] = {
  58. { 0x0090, 0x60000000 },
  59. { 0x0094, 0x60000000 },
  60. { 0x0098, 0x00800200 },
  61. { 0x009c, 0x00000000 },
  62. { 0x0020, 0x00000000 },
  63. { 0x0024, 0x00000000 },
  64. { 0x0028, 0x000244c8 },
  65. { 0x002c, 0x00000000 },
  66. { 0x0030, 0x00002400 },
  67. { 0x0034, 0x01520000 },
  68. { 0x0038, 0x00724003 },
  69. { 0x003c, 0x00000000 },
  70. { 0x0040, 0x00000000 },
  71. { 0x0044, 0x00000000 },
  72. { 0x0048, 0x00000000 },
  73. { 0x004c, 0x00000000 },
  74. { 0x0050, 0x00000000 },
  75. { 0x0054, 0x00000000 },
  76. { 0x0058, 0x00000000 },
  77. { 0x005c, 0x00000000 },
  78. { 0x0160, 0x00000000 },
  79. { 0x0004, 0xffffffff },
  80. { 0x0008, 0x00ec3fff },
  81. { 0x000c, 0x3bc001e7 },
  82. { 0x0010, 0x5bffffff },
  83. { 0x0014, 0x1ffffffb },
  84. { 0x0018, 0x01bffff0 },
  85. { 0x001c, 0xcf7fffff },
  86. { 0x0074, 0x0381fc00 },
  87. };
  88. static const struct reg_config pfc_without_unlock[] = {
  89. { 0x0100, 0xffffffdf },
  90. { 0x0104, 0xc883c3ff },
  91. { 0x0108, 0x1201f3c9 },
  92. { 0x010c, 0x00000000 },
  93. { 0x0110, 0xffffeb04 },
  94. { 0x0114, 0xc003ffff },
  95. { 0x0118, 0x0800000f },
  96. { 0x011c, 0x001800f0 },
  97. };
  98. static const u32 pfc_base = 0xe6060000;
  99. unsigned int i;
  100. for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
  101. writel(~pfc_with_unlock[i].val, pfc_base);
  102. writel(pfc_with_unlock[i].val,
  103. pfc_base | pfc_with_unlock[i].off);
  104. }
  105. for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
  106. writel(pfc_without_unlock[i].val,
  107. pfc_base | pfc_without_unlock[i].off);
  108. }
  109. static void spl_init_gpio(void)
  110. {
  111. static const u16 gpio_offs[] = {
  112. 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800
  113. };
  114. static const struct reg_config gpio_set[] = {
  115. { 0x2000, 0x04381000 },
  116. { 0x5000, 0x00000000 },
  117. { 0x5800, 0x000e0000 },
  118. };
  119. static const struct reg_config gpio_clr[] = {
  120. { 0x1000, 0x00000000 },
  121. { 0x2000, 0x04381010 },
  122. { 0x3000, 0x00000000 },
  123. { 0x4000, 0x00000000 },
  124. { 0x5000, 0x00400000 },
  125. { 0x5400, 0x00000000 },
  126. { 0x5800, 0x000e0380 },
  127. };
  128. static const u32 gpio_base = 0xe6050000;
  129. unsigned int i;
  130. for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
  131. writel(0, gpio_base | 0x20 | gpio_offs[i]);
  132. for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
  133. writel(0, gpio_base | 0x00 | gpio_offs[i]);
  134. for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
  135. writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
  136. for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
  137. writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
  138. }
  139. static void spl_init_lbsc(void)
  140. {
  141. static const struct reg_config lbsc_config[] = {
  142. { 0x00, 0x00000020 },
  143. { 0x08, 0x00002020 },
  144. { 0x30, 0x2a103320 },
  145. { 0x38, 0xff70ff70 },
  146. };
  147. static const u16 lbsc_offs[] = {
  148. 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
  149. };
  150. static const u32 lbsc_base = 0xfec00200;
  151. unsigned int i;
  152. for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
  153. writel(lbsc_config[i].val,
  154. lbsc_base | lbsc_config[i].off);
  155. writel(lbsc_config[i].val,
  156. lbsc_base | (lbsc_config[i].off + 4));
  157. }
  158. for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
  159. writel(0, lbsc_base | lbsc_offs[i]);
  160. }
  161. static void spl_init_dbsc(void)
  162. {
  163. static const struct reg_config dbsc_config1[] = {
  164. { 0x0018, 0x21000000 },
  165. { 0x0018, 0x11000000 },
  166. { 0x0018, 0x10000000 },
  167. { 0x0280, 0x0000a55a },
  168. { 0x0290, 0x00000010 },
  169. { 0x02a0, 0xf004649b },
  170. { 0x0020, 0x00000007 },
  171. { 0x0024, 0x0f030a02 },
  172. { 0x0030, 0x00000001 },
  173. { 0x00b0, 0x00000000 },
  174. { 0x0040, 0x0000000b },
  175. { 0x0044, 0x00000008 },
  176. { 0x0048, 0x00000000 },
  177. { 0x0050, 0x0000000b },
  178. { 0x0054, 0x000c000b },
  179. { 0x0058, 0x00000027 },
  180. { 0x005c, 0x0000001c },
  181. { 0x0060, 0x00000006 },
  182. { 0x0064, 0x00000020 },
  183. { 0x0068, 0x00000008 },
  184. { 0x006c, 0x0000000c },
  185. { 0x0070, 0x00000009 },
  186. { 0x0074, 0x00000012 },
  187. { 0x0078, 0x000000d0 },
  188. { 0x007c, 0x00140005 },
  189. { 0x0080, 0x00050004 },
  190. { 0x0084, 0x70233005 },
  191. { 0x0088, 0x000c0000 },
  192. { 0x008c, 0x00000300 },
  193. { 0x0090, 0x00000040 },
  194. { 0x0100, 0x00000001 },
  195. { 0x00c0, 0x00020001 },
  196. { 0x00c8, 0x20082008 },
  197. { 0x0380, 0x00020002 },
  198. { 0x0390, 0x0000001f },
  199. };
  200. static const struct reg_config dbsc_config5[] = {
  201. { 0x0244, 0x00000011 },
  202. { 0x0290, 0x00000006 },
  203. { 0x02a0, 0x0005c000 },
  204. { 0x0290, 0x00000003 },
  205. { 0x02a0, 0x0300c481 },
  206. { 0x0290, 0x00000023 },
  207. { 0x02a0, 0x00fdb6c0 },
  208. { 0x0290, 0x00000011 },
  209. { 0x02a0, 0x1000040b },
  210. { 0x0290, 0x00000012 },
  211. { 0x02a0, 0x9d9cbb66 },
  212. { 0x0290, 0x00000013 },
  213. { 0x02a0, 0x1a868400 },
  214. { 0x0290, 0x00000014 },
  215. { 0x02a0, 0x300214d8 },
  216. { 0x0290, 0x00000015 },
  217. { 0x02a0, 0x00000d70 },
  218. { 0x0290, 0x00000016 },
  219. { 0x02a0, 0x00000006 },
  220. { 0x0290, 0x00000017 },
  221. { 0x02a0, 0x00000018 },
  222. { 0x0290, 0x0000001a },
  223. { 0x02a0, 0x910035c7 },
  224. { 0x0290, 0x00000004 },
  225. };
  226. static const struct reg_config dbsc_config6[] = {
  227. { 0x0290, 0x00000001 },
  228. { 0x02a0, 0x00000181 },
  229. { 0x0018, 0x11000000 },
  230. { 0x0290, 0x00000004 },
  231. };
  232. static const struct reg_config dbsc_config7[] = {
  233. { 0x0290, 0x00000001 },
  234. { 0x02a0, 0x0000fe01 },
  235. { 0x0290, 0x00000004 },
  236. };
  237. static const struct reg_config dbsc_config8[] = {
  238. { 0x0304, 0x00000000 },
  239. { 0x00f4, 0x01004c20 },
  240. { 0x00f8, 0x014000aa },
  241. { 0x00e0, 0x00000140 },
  242. { 0x00e4, 0x00081860 },
  243. { 0x00e8, 0x00010000 },
  244. { 0x0014, 0x00000001 },
  245. { 0x0010, 0x00000001 },
  246. { 0x0280, 0x00000000 },
  247. };
  248. static const u32 dbsc3_0_base = DBSC3_0_BASE;
  249. static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
  250. unsigned int i;
  251. for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
  252. writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
  253. writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
  254. }
  255. dbsc_wait(0x240);
  256. for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
  257. writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
  258. writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
  259. }
  260. dbsc_wait(0x2a0);
  261. for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
  262. writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
  263. writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
  264. }
  265. dbsc_wait(0x2a0);
  266. for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
  267. writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
  268. writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
  269. }
  270. dbsc_wait(0x2a0);
  271. for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
  272. writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
  273. writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
  274. }
  275. }
  276. static void spl_init_qspi(void)
  277. {
  278. mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
  279. static const u32 qspi_base = 0xe6b10000;
  280. writeb(0x08, qspi_base + 0x00);
  281. writeb(0x00, qspi_base + 0x01);
  282. writeb(0x06, qspi_base + 0x02);
  283. writeb(0x01, qspi_base + 0x0a);
  284. writeb(0x00, qspi_base + 0x0b);
  285. writeb(0x00, qspi_base + 0x0c);
  286. writeb(0x00, qspi_base + 0x0d);
  287. writeb(0x00, qspi_base + 0x0e);
  288. writew(0xe080, qspi_base + 0x10);
  289. writeb(0xc0, qspi_base + 0x18);
  290. writeb(0x00, qspi_base + 0x18);
  291. writeb(0x00, qspi_base + 0x08);
  292. writeb(0x48, qspi_base + 0x00);
  293. }
  294. void board_init_f(ulong dummy)
  295. {
  296. int i;
  297. mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  298. mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
  299. /*
  300. * SD0 clock is set to 97.5MHz by default.
  301. * Set SD2 to the 97.5MHz as well.
  302. */
  303. writel(SD_97500KHZ, SD2CKCR);
  304. spl_init_sys();
  305. spl_init_pfc();
  306. spl_init_gpio();
  307. spl_init_lbsc();
  308. /* Unknown, likely ES1.0-specific delay */
  309. for (i = 0; i < 100000; i++)
  310. asm volatile("nop");
  311. spl_init_dbsc();
  312. spl_init_qspi();
  313. }
  314. void spl_board_init(void)
  315. {
  316. /* UART clocks enabled and gd valid - init serial console */
  317. preloader_console_init();
  318. }
  319. void board_boot_order(u32 *spl_boot_list)
  320. {
  321. const u32 jtag_magic = 0x1337c0de;
  322. const u32 load_magic = 0xb33fc0de;
  323. /*
  324. * If JTAG probe sets special word at 0xe6300020, then it must
  325. * put U-Boot into RAM and SPL will start it from RAM.
  326. */
  327. if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
  328. printf("JTAG boot detected!\n");
  329. while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
  330. ;
  331. spl_boot_list[0] = BOOT_DEVICE_RAM;
  332. spl_boot_list[1] = BOOT_DEVICE_NONE;
  333. return;
  334. }
  335. /* Boot from SPI NOR with YMODEM UART fallback. */
  336. spl_boot_list[0] = BOOT_DEVICE_SPI;
  337. spl_boot_list[1] = BOOT_DEVICE_UART;
  338. spl_boot_list[2] = BOOT_DEVICE_NONE;
  339. }
  340. void reset_cpu(ulong addr)
  341. {
  342. }