eagle.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board/renesas/eagle/eagle.c
  4. * This file is Eagle board support.
  5. *
  6. * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <malloc.h>
  11. #include <netdev.h>
  12. #include <dm.h>
  13. #include <dm/platform_data/serial_sh.h>
  14. #include <asm/processor.h>
  15. #include <asm/mach-types.h>
  16. #include <asm/io.h>
  17. #include <linux/errno.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/gpio.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/rmobile.h>
  22. #include <asm/arch/rcar-mstp.h>
  23. #include <asm/arch/sh_sdhi.h>
  24. #include <i2c.h>
  25. #include <mmc.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define CPGWPR 0xE6150900
  28. #define CPGWPCR 0xE6150904
  29. /* PLL */
  30. #define PLL0CR 0xE61500D8
  31. #define PLL0_STC_MASK 0x7F000000
  32. #define PLL0_STC_OFFSET 24
  33. #define CLK2MHZ(clk) (clk / 1000 / 1000)
  34. void s_init(void)
  35. {
  36. struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  37. struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  38. u32 stc;
  39. /* Watchdog init */
  40. writel(0xA5A5A500, &rwdt->rwtcsra);
  41. writel(0xA5A5A500, &swdt->swtcsra);
  42. /* CPU frequency setting. Set to 0.8GHz */
  43. stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
  44. clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
  45. }
  46. int board_early_init_f(void)
  47. {
  48. /* Unlock CPG access */
  49. writel(0xA5A5FFFF, CPGWPR);
  50. writel(0x5A5A0000, CPGWPCR);
  51. return 0;
  52. }
  53. int board_init(void)
  54. {
  55. /* adress of boot parameters */
  56. gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
  57. return 0;
  58. }
  59. #define RST_BASE 0xE6160000
  60. #define RST_CA57RESCNT (RST_BASE + 0x40)
  61. #define RST_CA53RESCNT (RST_BASE + 0x44)
  62. #define RST_RSTOUTCR (RST_BASE + 0x58)
  63. #define RST_CA57_CODE 0xA5A5000F
  64. #define RST_CA53_CODE 0x5A5A000F
  65. void reset_cpu(ulong addr)
  66. {
  67. unsigned long midr, cputype;
  68. asm volatile("mrs %0, midr_el1" : "=r" (midr));
  69. cputype = (midr >> 4) & 0xfff;
  70. if (cputype == 0xd03)
  71. writel(RST_CA53_CODE, RST_CA53RESCNT);
  72. else if (cputype == 0xd07)
  73. writel(RST_CA57_CODE, RST_CA57RESCNT);
  74. else
  75. hang();
  76. }