alt.c 2.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * board/renesas/alt/alt.c
  4. *
  5. * Copyright (C) 2014, 2015 Renesas Electronics Corporation
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <env.h>
  10. #include <malloc.h>
  11. #include <dm.h>
  12. #include <dm/platform_data/serial_sh.h>
  13. #include <env_internal.h>
  14. #include <asm/processor.h>
  15. #include <asm/mach-types.h>
  16. #include <asm/io.h>
  17. #include <linux/errno.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/gpio.h>
  20. #include <asm/arch/rmobile.h>
  21. #include <asm/arch/rcar-mstp.h>
  22. #include <asm/arch/mmc.h>
  23. #include <asm/arch/sh_sdhi.h>
  24. #include <netdev.h>
  25. #include <miiphy.h>
  26. #include <i2c.h>
  27. #include <div64.h>
  28. #include "qos.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. void s_init(void)
  31. {
  32. struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
  33. struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
  34. /* Watchdog init */
  35. writel(0xA5A5A500, &rwdt->rwtcsra);
  36. writel(0xA5A5A500, &swdt->swtcsra);
  37. /* QoS */
  38. qos_init();
  39. }
  40. #define TMU0_MSTP125 BIT(25)
  41. #define MMC0_MSTP315 BIT(15)
  42. #define SD1CKCR 0xE6150078
  43. #define SD_97500KHZ 0x7
  44. int board_early_init_f(void)
  45. {
  46. /* TMU */
  47. mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
  48. /* Set SD1 to the 97.5MHz */
  49. writel(SD_97500KHZ, SD1CKCR);
  50. return 0;
  51. }
  52. #define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */
  53. int board_init(void)
  54. {
  55. /* adress of boot parameters */
  56. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  57. /* Force ethernet PHY out of reset */
  58. gpio_request(ETHERNET_PHY_RESET, "phy_reset");
  59. gpio_direction_output(ETHERNET_PHY_RESET, 0);
  60. mdelay(20);
  61. gpio_direction_output(ETHERNET_PHY_RESET, 1);
  62. udelay(1);
  63. return 0;
  64. }
  65. int dram_init(void)
  66. {
  67. if (fdtdec_setup_mem_size_base() != 0)
  68. return -EINVAL;
  69. return 0;
  70. }
  71. int dram_init_banksize(void)
  72. {
  73. fdtdec_setup_memory_banksize();
  74. return 0;
  75. }
  76. /* KSZ8041RNLI */
  77. #define PHY_CONTROL1 0x1E
  78. #define PHY_LED_MODE 0xC000
  79. #define PHY_LED_MODE_ACK 0x4000
  80. int board_phy_config(struct phy_device *phydev)
  81. {
  82. int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
  83. ret &= ~PHY_LED_MODE;
  84. ret |= PHY_LED_MODE_ACK;
  85. ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
  86. return 0;
  87. }
  88. void reset_cpu(ulong addr)
  89. {
  90. struct udevice *dev;
  91. const u8 pmic_bus = 7;
  92. const u8 pmic_addr = 0x58;
  93. u8 data;
  94. int ret;
  95. ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
  96. if (ret)
  97. hang();
  98. ret = dm_i2c_read(dev, 0x13, &data, 1);
  99. if (ret)
  100. hang();
  101. data |= BIT(1);
  102. ret = dm_i2c_write(dev, 0x13, &data, 1);
  103. if (ret)
  104. hang();
  105. }
  106. enum env_location env_get_location(enum env_operation op, int prio)
  107. {
  108. const u32 load_magic = 0xb33fc0de;
  109. /* Block environment access if loaded using JTAG */
  110. if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
  111. (op != ENVOP_INIT))
  112. return ENVL_UNKNOWN;
  113. if (prio)
  114. return ENVL_UNKNOWN;
  115. return ENVL_SPI_FLASH;
  116. }