spl.c 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159
  1. /*
  2. * Copyright 2018-2019 NXP
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <spl.h>
  9. #include <asm/io.h>
  10. #include <errno.h>
  11. #include <asm/io.h>
  12. #include <asm/mach-imx/iomux-v3.h>
  13. #include <asm/arch/imx8mp_pins.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <power/pmic.h>
  17. #include <power/pca9450.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/mach-imx/gpio.h>
  20. #include <asm/mach-imx/mxc_i2c.h>
  21. #include <fsl_esdhc.h>
  22. #include <mmc.h>
  23. #include <asm/arch/ddr.h>
  24. #include <dm/uclass.h>
  25. #include <dm/device.h>
  26. #include <dm/uclass-internal.h>
  27. #include <dm/device-internal.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. int spl_board_boot_device(enum boot_device boot_dev_spl)
  30. {
  31. return BOOT_DEVICE_BOOTROM;
  32. }
  33. void spl_dram_init(void)
  34. {
  35. ddr_init(&dram_timing);
  36. }
  37. void spl_board_init(void)
  38. {
  39. struct udevice *dev;
  40. int ret;
  41. puts("Normal Boot\n");
  42. ret = uclass_get_device_by_name(UCLASS_CLK,
  43. "clock-controller@30380000",
  44. &dev);
  45. if (ret < 0)
  46. printf("Failed to find clock node. Check device tree\n");
  47. }
  48. #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
  49. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  50. struct i2c_pads_info i2c_pad_info1 = {
  51. .scl = {
  52. .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
  53. .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  54. .gp = IMX_GPIO_NR(5, 14),
  55. },
  56. .sda = {
  57. .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
  58. .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  59. .gp = IMX_GPIO_NR(5, 15),
  60. },
  61. };
  62. #ifdef CONFIG_POWER
  63. #define I2C_PMIC 0
  64. int power_init_board(void)
  65. {
  66. struct pmic *p;
  67. int ret;
  68. ret = power_pca9450b_init(I2C_PMIC);
  69. if (ret)
  70. printf("power init failed");
  71. p = pmic_get("PCA9450");
  72. pmic_probe(p);
  73. /* BUCKxOUT_DVS0/1 control BUCK123 output */
  74. pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
  75. /*
  76. * increase VDD_SOC to typical value 0.95V before first
  77. * DRAM access, set DVS1 to 0.85v for suspend.
  78. * Enable DVS control through PMIC_STBY_REQ and
  79. * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
  80. */
  81. pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
  82. pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
  83. pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
  84. /* set WDOG_B_CFG to cold reset */
  85. pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
  86. return 0;
  87. }
  88. #endif
  89. #ifdef CONFIG_SPL_LOAD_FIT
  90. int board_fit_config_name_match(const char *name)
  91. {
  92. /* Just empty function now - can't decide what to choose */
  93. debug("%s: %s\n", __func__, name);
  94. return 0;
  95. }
  96. #endif
  97. void board_init_f(ulong dummy)
  98. {
  99. int ret;
  100. arch_cpu_init();
  101. init_uart_clk(1);
  102. board_early_init_f();
  103. timer_init();
  104. preloader_console_init();
  105. /* Clear the BSS. */
  106. memset(__bss_start, 0, __bss_end - __bss_start);
  107. ret = spl_init();
  108. if (ret) {
  109. debug("spl_init() failed: %d\n", ret);
  110. hang();
  111. }
  112. enable_tzc380();
  113. /* Adjust pmic voltage to 1.0V for 800M */
  114. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  115. power_init_board();
  116. /* DDR initialization */
  117. spl_dram_init();
  118. board_init_r(NULL, 0);
  119. }
  120. int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  121. {
  122. puts("resetting ...\n");
  123. reset_cpu(WDOG1_BASE_ADDR);
  124. return 0;
  125. }