soc.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <cpu_func.h>
  6. #include <init.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/mach-imx/boot_mode.h>
  12. #include <asm/mach-imx/hab.h>
  13. #define PMC0_BASE_ADDR 0x410a1000
  14. #define PMC0_CTRL 0x28
  15. #define PMC0_CTRL_LDOEN BIT(31)
  16. #define PMC0_CTRL_LDOOKDIS BIT(30)
  17. #define PMC0_CTRL_PMC1ON BIT(24)
  18. #define PMC1_BASE_ADDR 0x40400000
  19. #define PMC1_RUN 0x8
  20. #define PMC1_STOP 0x10
  21. #define PMC1_VLPS 0x14
  22. #define PMC1_LDOVL_SHIFT 16
  23. #define PMC1_LDOVL_MASK (0x3f << PMC1_LDOVL_SHIFT)
  24. #define PMC1_LDOVL_900 0x1e
  25. #define PMC1_LDOVL_950 0x23
  26. #define PMC1_STATUS 0x20
  27. #define PMC1_STATUS_LDOVLF BIT(8)
  28. static char *get_reset_cause(char *);
  29. #if defined(CONFIG_IMX_HAB)
  30. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  31. .bank = 29,
  32. .word = 6,
  33. };
  34. #endif
  35. #define ROM_VERSION_ADDR 0x80
  36. u32 get_cpu_rev(void)
  37. {
  38. /* Check the ROM version for cpu revision */
  39. u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR);
  40. return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF);
  41. }
  42. #ifdef CONFIG_REVISION_TAG
  43. u32 __weak get_board_rev(void)
  44. {
  45. return get_cpu_rev();
  46. }
  47. #endif
  48. enum bt_mode get_boot_mode(void)
  49. {
  50. u32 bt0_cfg = 0;
  51. bt0_cfg = readl(CMC0_RBASE + 0x40);
  52. bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK);
  53. if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) {
  54. /* No low power boot */
  55. if (bt0_cfg & BT0CFG_DUALBOOT_MASK)
  56. return DUAL_BOOT;
  57. else
  58. return SINGLE_BOOT;
  59. }
  60. return LOW_POWER_BOOT;
  61. }
  62. int arch_cpu_init(void)
  63. {
  64. return 0;
  65. }
  66. #ifdef CONFIG_BOARD_POSTCLK_INIT
  67. int board_postclk_init(void)
  68. {
  69. return 0;
  70. }
  71. #endif
  72. #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
  73. #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
  74. #define REFRESH_WORD0 0xA602 /* 1st refresh word */
  75. #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
  76. static void disable_wdog(u32 wdog_base)
  77. {
  78. writel(UNLOCK_WORD0, (wdog_base + 0x04));
  79. writel(UNLOCK_WORD1, (wdog_base + 0x04));
  80. writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
  81. writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
  82. writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
  83. writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
  84. writel(REFRESH_WORD1, (wdog_base + 0x04));
  85. }
  86. void init_wdog(void)
  87. {
  88. /*
  89. * ROM will configure WDOG1, disable it or enable it
  90. * depending on FUSE. The update bit is set for reconfigurable.
  91. * We have to use unlock sequence to reconfigure it.
  92. * WDOG2 is not touched by ROM, so it will have default value
  93. * which is enabled. We can directly configure it.
  94. * To simplify the codes, we still use same reconfigure
  95. * process as WDOG1. Because the update bit is not set for
  96. * WDOG2, the unlock sequence won't take effect really.
  97. * It actually directly configure the wdog.
  98. * In this function, we will disable both WDOG1 and WDOG2,
  99. * and set update bit for both. So that kernel can reconfigure them.
  100. */
  101. disable_wdog(WDG1_RBASE);
  102. disable_wdog(WDG2_RBASE);
  103. }
  104. #if defined(CONFIG_LDO_ENABLED_MODE)
  105. static void init_ldo_mode(void)
  106. {
  107. unsigned int reg;
  108. /* Set LDOOKDIS */
  109. setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
  110. /* Set LDOVL to 0.95V in PMC1_RUN */
  111. reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
  112. reg &= ~PMC1_LDOVL_MASK;
  113. reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
  114. writel(PMC1_BASE_ADDR + PMC1_RUN, reg);
  115. /* Wait for LDOVLF to be cleared */
  116. reg = readl(PMC1_BASE_ADDR + PMC1_STATUS);
  117. while (reg & PMC1_STATUS_LDOVLF)
  118. ;
  119. /* Set LDOVL to 0.95V in PMC1_STOP */
  120. reg = readl(PMC1_BASE_ADDR + PMC1_STOP);
  121. reg &= ~PMC1_LDOVL_MASK;
  122. reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
  123. writel(PMC1_BASE_ADDR + PMC1_STOP, reg);
  124. /* Set LDOVL to 0.90V in PMC1_VLPS */
  125. reg = readl(PMC1_BASE_ADDR + PMC1_VLPS);
  126. reg &= ~PMC1_LDOVL_MASK;
  127. reg |= (PMC1_LDOVL_900 << PMC1_LDOVL_SHIFT);
  128. writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
  129. /* Set LDOEN bit */
  130. setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
  131. /* Set the PMC1ON bit */
  132. setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
  133. }
  134. #endif
  135. void s_init(void)
  136. {
  137. /* Disable wdog */
  138. init_wdog();
  139. /* clock configuration. */
  140. clock_init();
  141. if (soc_rev() < CHIP_REV_2_0) {
  142. /* enable dumb pmic */
  143. writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
  144. }
  145. #if defined(CONFIG_LDO_ENABLED_MODE)
  146. init_ldo_mode();
  147. #endif
  148. return;
  149. }
  150. #ifndef CONFIG_ULP_WATCHDOG
  151. void reset_cpu(ulong addr)
  152. {
  153. setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
  154. while (1)
  155. ;
  156. }
  157. #endif
  158. #if defined(CONFIG_DISPLAY_CPUINFO)
  159. const char *get_imx_type(u32 imxtype)
  160. {
  161. return "7ULP";
  162. }
  163. #define PMC0_BASE_ADDR 0x410a1000
  164. #define PMC0_CTRL 0x28
  165. #define PMC0_CTRL_LDOEN BIT(31)
  166. static bool ldo_mode_is_enabled(void)
  167. {
  168. unsigned int reg;
  169. reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
  170. if (reg & PMC0_CTRL_LDOEN)
  171. return true;
  172. else
  173. return false;
  174. }
  175. int print_cpuinfo(void)
  176. {
  177. u32 cpurev;
  178. char cause[18];
  179. cpurev = get_cpu_rev();
  180. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  181. get_imx_type((cpurev & 0xFF000) >> 12),
  182. (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
  183. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  184. printf("Reset cause: %s\n", get_reset_cause(cause));
  185. printf("Boot mode: ");
  186. switch (get_boot_mode()) {
  187. case LOW_POWER_BOOT:
  188. printf("Low power boot\n");
  189. break;
  190. case DUAL_BOOT:
  191. printf("Dual boot\n");
  192. break;
  193. case SINGLE_BOOT:
  194. default:
  195. printf("Single boot\n");
  196. break;
  197. }
  198. if (ldo_mode_is_enabled())
  199. printf("PMC1: LDO enabled mode\n");
  200. else
  201. printf("PMC1: LDO bypass mode\n");
  202. return 0;
  203. }
  204. #endif
  205. #define CMC_SRS_TAMPER (1 << 31)
  206. #define CMC_SRS_SECURITY (1 << 30)
  207. #define CMC_SRS_TZWDG (1 << 29)
  208. #define CMC_SRS_JTAG_RST (1 << 28)
  209. #define CMC_SRS_CORE1 (1 << 16)
  210. #define CMC_SRS_LOCKUP (1 << 15)
  211. #define CMC_SRS_SW (1 << 14)
  212. #define CMC_SRS_WDG (1 << 13)
  213. #define CMC_SRS_PIN_RESET (1 << 8)
  214. #define CMC_SRS_WARM (1 << 4)
  215. #define CMC_SRS_HVD (1 << 3)
  216. #define CMC_SRS_LVD (1 << 2)
  217. #define CMC_SRS_POR (1 << 1)
  218. #define CMC_SRS_WUP (1 << 0)
  219. static u32 reset_cause = -1;
  220. static char *get_reset_cause(char *ret)
  221. {
  222. u32 cause1, cause = 0, srs = 0;
  223. u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
  224. u32 *reg_srs = (u32 *)(SRC_BASE_ADDR + 0x20);
  225. if (!ret)
  226. return "null";
  227. srs = readl(reg_srs);
  228. cause1 = readl(reg_ssrs);
  229. writel(cause1, reg_ssrs);
  230. reset_cause = cause1;
  231. cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM);
  232. switch (cause) {
  233. case CMC_SRS_POR:
  234. sprintf(ret, "%s", "POR");
  235. break;
  236. case CMC_SRS_WUP:
  237. sprintf(ret, "%s", "WUP");
  238. break;
  239. case CMC_SRS_WARM:
  240. cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW |
  241. CMC_SRS_JTAG_RST);
  242. switch (cause) {
  243. case CMC_SRS_WDG:
  244. sprintf(ret, "%s", "WARM-WDG");
  245. break;
  246. case CMC_SRS_SW:
  247. sprintf(ret, "%s", "WARM-SW");
  248. break;
  249. case CMC_SRS_JTAG_RST:
  250. sprintf(ret, "%s", "WARM-JTAG");
  251. break;
  252. default:
  253. sprintf(ret, "%s", "WARM-UNKN");
  254. break;
  255. }
  256. break;
  257. default:
  258. sprintf(ret, "%s-%X", "UNKN", cause1);
  259. break;
  260. }
  261. debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1);
  262. return ret;
  263. }
  264. #ifdef CONFIG_ENV_IS_IN_MMC
  265. __weak int board_mmc_get_env_dev(int devno)
  266. {
  267. return CONFIG_SYS_MMC_ENV_DEV;
  268. }
  269. int mmc_get_env_dev(void)
  270. {
  271. int devno = 0;
  272. u32 bt1_cfg = 0;
  273. /* If not boot from sd/mmc, use default value */
  274. if (get_boot_mode() == LOW_POWER_BOOT)
  275. return CONFIG_SYS_MMC_ENV_DEV;
  276. bt1_cfg = readl(CMC1_RBASE + 0x40);
  277. devno = (bt1_cfg >> 9) & 0x7;
  278. return board_mmc_get_env_dev(devno);
  279. }
  280. #endif
  281. enum boot_device get_boot_device(void)
  282. {
  283. struct bootrom_sw_info **p =
  284. (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
  285. enum boot_device boot_dev = SD1_BOOT;
  286. u8 boot_type = (*p)->boot_dev_type;
  287. u8 boot_instance = (*p)->boot_dev_instance;
  288. switch (boot_type) {
  289. case BOOT_TYPE_SD:
  290. boot_dev = boot_instance + SD1_BOOT;
  291. break;
  292. case BOOT_TYPE_MMC:
  293. boot_dev = boot_instance + MMC1_BOOT;
  294. break;
  295. case BOOT_TYPE_USB:
  296. boot_dev = USB_BOOT;
  297. break;
  298. default:
  299. break;
  300. }
  301. return boot_dev;
  302. }