k3-j721e-mcu-wakeup.dtsi 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
  4. *
  5. * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
  6. */
  7. &cbass_mcu_wakeup {
  8. dmsc: dmsc@44083000 {
  9. compatible = "ti,k2g-sci";
  10. ti,host-id = <12>;
  11. mbox-names = "rx", "tx";
  12. mboxes= <&secure_proxy_main 11>,
  13. <&secure_proxy_main 13>;
  14. reg-names = "debug_messages";
  15. reg = <0x00 0x44083000 0x0 0x1000>;
  16. k3_pds: power-controller {
  17. compatible = "ti,sci-pm-domain";
  18. #power-domain-cells = <2>;
  19. };
  20. k3_clks: clocks {
  21. compatible = "ti,k2g-sci-clk";
  22. #clock-cells = <2>;
  23. ti,scan-clocks-from-dt;
  24. };
  25. k3_reset: reset-controller {
  26. compatible = "ti,sci-reset";
  27. #reset-cells = <2>;
  28. };
  29. };
  30. wkup_pmx0: pinmux@4301c000 {
  31. compatible = "pinctrl-single";
  32. /* Proxy 0 addressing */
  33. reg = <0x00 0x4301c000 0x00 0x178>;
  34. #pinctrl-cells = <1>;
  35. pinctrl-single,register-width = <32>;
  36. pinctrl-single,function-mask = <0xffffffff>;
  37. };
  38. wkup_uart0: serial@42300000 {
  39. compatible = "ti,j721e-uart", "ti,am654-uart";
  40. reg = <0x00 0x42300000 0x00 0x100>;
  41. reg-shift = <2>;
  42. reg-io-width = <4>;
  43. interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
  44. clock-frequency = <48000000>;
  45. current-speed = <115200>;
  46. power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
  47. clocks = <&k3_clks 287 0>;
  48. clock-names = "fclk";
  49. };
  50. wkup_i2c0: i2c@42120000 {
  51. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  52. reg = <0x0 0x42120000 0x0 0x100>;
  53. interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
  54. #address-cells = <1>;
  55. #size-cells = <0>;
  56. clock-names = "fck";
  57. clocks = <&k3_clks 197 0>;
  58. power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
  59. };
  60. mcu_uart0: serial@40a00000 {
  61. compatible = "ti,j721e-uart", "ti,am654-uart";
  62. reg = <0x00 0x40a00000 0x00 0x100>;
  63. reg-shift = <2>;
  64. reg-io-width = <4>;
  65. interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
  66. clock-frequency = <96000000>;
  67. current-speed = <115200>;
  68. power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
  69. clocks = <&k3_clks 149 0>;
  70. clock-names = "fclk";
  71. };
  72. mcu_r5fss0: r5fss@41000000 {
  73. compatible = "ti,j721e-r5fss";
  74. lockstep-mode = <1>;
  75. #address-cells = <1>;
  76. #size-cells = <1>;
  77. ranges = <0x41000000 0x00 0x41000000 0x20000>,
  78. <0x41400000 0x00 0x41400000 0x20000>;
  79. power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
  80. mcu_r5fss0_core0: r5f@41000000 {
  81. compatible = "ti,j721e-r5f";
  82. reg = <0x41000000 0x00008000>,
  83. <0x41010000 0x00008000>;
  84. reg-names = "atcm", "btcm";
  85. ti,sci = <&dmsc>;
  86. ti,sci-dev-id = <250>;
  87. ti,sci-proc-ids = <0x01 0xFF>;
  88. resets = <&k3_reset 250 1>;
  89. atcm-enable = <1>;
  90. btcm-enable = <1>;
  91. loczrama = <1>;
  92. };
  93. mcu_r5fss0_core1: r5f@41400000 {
  94. compatible = "ti,j721e-r5f";
  95. reg = <0x41400000 0x00008000>,
  96. <0x41410000 0x00008000>;
  97. reg-names = "atcm", "btcm";
  98. ti,sci = <&dmsc>;
  99. ti,sci-dev-id = <251>;
  100. ti,sci-proc-ids = <0x02 0xFF>;
  101. resets = <&k3_reset 251 1>;
  102. atcm-enable = <1>;
  103. btcm-enable = <1>;
  104. loczrama = <1>;
  105. };
  106. };
  107. fss: fss@47000000 {
  108. compatible = "syscon", "simple-mfd";
  109. reg = <0x0 0x47000000 0x0 0x100>;
  110. #address-cells = <2>;
  111. #size-cells = <2>;
  112. ranges;
  113. hbmc_mux: hbmc-mux {
  114. compatible = "mmio-mux";
  115. #mux-control-cells = <1>;
  116. mux-reg-masks = <0x4 0x2>; /* HBMC select */
  117. };
  118. hbmc: hyperbus@47034000 {
  119. compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
  120. reg = <0x0 0x47034000 0x0 0x100>,
  121. <0x5 0x00000000 0x1 0x0000000>;
  122. power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
  123. #address-cells = <2>;
  124. #size-cells = <1>;
  125. mux-controls = <&hbmc_mux 0>;
  126. assigned-clocks = <&k3_clks 102 0>;
  127. assigned-clock-rates = <250000000>;
  128. };
  129. ospi0: spi@47040000 {
  130. compatible = "ti,am654-ospi";
  131. reg = <0x0 0x47040000 0x0 0x100>,
  132. <0x5 0x00000000 0x1 0x0000000>;
  133. interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
  134. cdns,fifo-depth = <256>;
  135. cdns,fifo-width = <4>;
  136. cdns,trigger-address = <0x0>;
  137. clocks = <&k3_clks 103 0>;
  138. assigned-clocks = <&k3_clks 103 0>;
  139. assigned-clock-parents = <&k3_clks 103 2>;
  140. assigned-clock-rates = <166666666>;
  141. power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
  142. #address-cells = <1>;
  143. #size-cells = <0>;
  144. };
  145. ospi1: spi@47050000 {
  146. compatible = "ti,am654-ospi";
  147. reg = <0x0 0x47050000 0x0 0x100>,
  148. <0x7 0x00000000 0x1 0x00000000>;
  149. interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
  150. cdns,fifo-depth = <256>;
  151. cdns,fifo-width = <4>;
  152. cdns,trigger-address = <0x0>;
  153. clocks = <&k3_clks 104 0>;
  154. assigned-clocks = <&k3_clks 104 0>;
  155. assigned-clock-rates = <133333333>;
  156. power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
  157. #address-cells = <1>;
  158. #size-cells = <0>;
  159. };
  160. };
  161. mcu_i2c0: i2c@40b00000 {
  162. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  163. reg = <0x0 0x40b00000 0x0 0x100>;
  164. interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
  165. #address-cells = <1>;
  166. #size-cells = <0>;
  167. clock-names = "fck";
  168. clocks = <&k3_clks 194 0>;
  169. power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
  170. };
  171. mcu_i2c1: i2c@40b10000 {
  172. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  173. reg = <0x0 0x40b10000 0x0 0x100>;
  174. interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
  175. #address-cells = <1>;
  176. #size-cells = <0>;
  177. clock-names = "fck";
  178. clocks = <&k3_clks 195 0>;
  179. power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
  180. };
  181. mcu_navss {
  182. compatible = "simple-mfd";
  183. #address-cells = <2>;
  184. #size-cells = <2>;
  185. ranges;
  186. dma-coherent;
  187. dma-ranges;
  188. ti,sci-dev-id = <232>;
  189. mcu_ringacc: ringacc@2b800000 {
  190. compatible = "ti,am654-navss-ringacc";
  191. reg = <0x0 0x2b800000 0x0 0x400000>,
  192. <0x0 0x2b000000 0x0 0x400000>,
  193. <0x0 0x28590000 0x0 0x100>,
  194. <0x0 0x2a500000 0x0 0x40000>;
  195. reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
  196. ti,num-rings = <286>;
  197. ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
  198. ti,sci = <&dmsc>;
  199. ti,sci-dev-id = <235>;
  200. };
  201. mcu_udmap: dma-controller@285c0000 {
  202. compatible = "ti,j721e-navss-mcu-udmap";
  203. reg = <0x0 0x285c0000 0x0 0x100>,
  204. <0x0 0x2a800000 0x0 0x40000>,
  205. <0x0 0x2aa00000 0x0 0x40000>;
  206. reg-names = "gcfg", "rchanrt", "tchanrt";
  207. #dma-cells = <1>;
  208. ti,sci = <&dmsc>;
  209. ti,sci-dev-id = <236>;
  210. ti,ringacc = <&mcu_ringacc>;
  211. ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
  212. <0x0f>; /* TX_HCHAN */
  213. ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
  214. <0x0b>; /* RX_HCHAN */
  215. ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
  216. };
  217. };
  218. };