k3-j721e-common-proc-board-u-boot.dtsi 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  4. */
  5. #include <dt-bindings/net/ti-dp83867.h>
  6. / {
  7. chosen {
  8. stdout-path = "serial2:115200n8";
  9. tick-timer = &timer1;
  10. };
  11. aliases {
  12. ethernet0 = &cpsw_port1;
  13. };
  14. };
  15. &cbass_main{
  16. u-boot,dm-spl;
  17. };
  18. &cbass_mcu_wakeup {
  19. u-boot,dm-spl;
  20. timer1: timer@40400000 {
  21. compatible = "ti,omap5430-timer";
  22. reg = <0x0 0x40400000 0x0 0x80>;
  23. ti,timer-alwon;
  24. clock-frequency = <25000000>;
  25. u-boot,dm-spl;
  26. };
  27. mcu_conf: scm_conf@40f00000 {
  28. compatible = "syscon", "simple-mfd";
  29. reg = <0x0 0x40f00000 0x0 0x20000>;
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. ranges = <0x0 0x0 0x40f00000 0x20000>;
  33. phy_sel: cpsw-phy-sel@4040 {
  34. compatible = "ti,am654-cpsw-phy-sel";
  35. reg = <0x4040 0x4>;
  36. reg-names = "gmii-sel";
  37. };
  38. };
  39. mcu_navss {
  40. u-boot,dm-spl;
  41. ringacc@2b800000 {
  42. u-boot,dm-spl;
  43. };
  44. dma-controller@285c0000 {
  45. u-boot,dm-spl;
  46. };
  47. };
  48. mcu_cpsw: ethernet@046000000 {
  49. compatible = "ti,j721e-cpsw-nuss";
  50. #address-cells = <2>;
  51. #size-cells = <2>;
  52. reg = <0x0 0x46000000 0x0 0x200000>;
  53. reg-names = "cpsw_nuss";
  54. ranges;
  55. dma-coherent;
  56. clocks = <&k3_clks 18 22>;
  57. clock-names = "fck";
  58. power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
  59. cpsw-phy-sel = <&phy_sel>;
  60. dmas = <&mcu_udmap 0xf000>,
  61. <&mcu_udmap 0xf001>,
  62. <&mcu_udmap 0xf002>,
  63. <&mcu_udmap 0xf003>,
  64. <&mcu_udmap 0xf004>,
  65. <&mcu_udmap 0xf005>,
  66. <&mcu_udmap 0xf006>,
  67. <&mcu_udmap 0xf007>,
  68. <&mcu_udmap 0x7000>;
  69. dma-names = "tx0", "tx1", "tx2", "tx3",
  70. "tx4", "tx5", "tx6", "tx7",
  71. "rx";
  72. ports {
  73. #address-cells = <1>;
  74. #size-cells = <0>;
  75. host: host@0 {
  76. reg = <0>;
  77. ti,label = "host";
  78. };
  79. cpsw_port1: port@1 {
  80. reg = <1>;
  81. ti,mac-only;
  82. ti,label = "port1";
  83. ti,syscon-efuse = <&mcu_conf 0x200>;
  84. };
  85. };
  86. davinci_mdio: mdio {
  87. #address-cells = <1>;
  88. #size-cells = <0>;
  89. bus_freq = <1000000>;
  90. };
  91. cpts {
  92. clocks = <&k3_clks 18 2>;
  93. clock-names = "cpts";
  94. interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
  95. interrupt-names = "cpts";
  96. ti,cpts-ext-ts-inputs = <4>;
  97. ti,cpts-periodic-outputs = <2>;
  98. };
  99. };
  100. };
  101. &secure_proxy_main {
  102. u-boot,dm-spl;
  103. };
  104. &dmsc {
  105. u-boot,dm-spl;
  106. k3_sysreset: sysreset-controller {
  107. compatible = "ti,sci-sysreset";
  108. u-boot,dm-spl;
  109. };
  110. };
  111. &k3_pds {
  112. u-boot,dm-spl;
  113. };
  114. &k3_clks {
  115. u-boot,dm-spl;
  116. };
  117. &k3_reset {
  118. u-boot,dm-spl;
  119. };
  120. &wkup_pmx0 {
  121. u-boot,dm-spl;
  122. mcu_cpsw_pins_default: mcu_cpsw_pins_default {
  123. pinctrl-single,pins = <
  124. J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
  125. J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
  126. J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
  127. J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
  128. J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
  129. J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
  130. J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
  131. J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
  132. J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
  133. J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
  134. J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
  135. J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
  136. >;
  137. };
  138. mcu_mdio_pins_default: mcu_mdio1_pins_default {
  139. pinctrl-single,pins = <
  140. J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
  141. J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
  142. >;
  143. };
  144. };
  145. &main_pmx0 {
  146. u-boot,dm-spl;
  147. };
  148. &main_uart0 {
  149. u-boot,dm-spl;
  150. };
  151. &mcu_uart0 {
  152. u-boot,dm-spl;
  153. };
  154. &main_sdhci0 {
  155. u-boot,dm-spl;
  156. };
  157. &main_sdhci1 {
  158. u-boot,dm-spl;
  159. };
  160. &main_usbss0_pins_default {
  161. u-boot,dm-spl;
  162. };
  163. &usbss0 {
  164. u-boot,dm-spl;
  165. ti,usb2-only;
  166. };
  167. &usb0 {
  168. dr_mode = "peripheral";
  169. u-boot,dm-spl;
  170. };
  171. &mcu_cpsw {
  172. pinctrl-names = "default";
  173. pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
  174. };
  175. &davinci_mdio {
  176. phy0: ethernet-phy@0 {
  177. reg = <0>;
  178. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  179. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  180. };
  181. };
  182. &cpsw_port1 {
  183. phy-mode = "rgmii-rxid";
  184. phy-handle = <&phy0>;
  185. };
  186. &mcu_cpsw {
  187. reg = <0x0 0x46000000 0x0 0x200000>,
  188. <0x0 0x40f00200 0x0 0x2>;
  189. reg-names = "cpsw_nuss", "mac_efuse";
  190. cpsw-phy-sel@40f04040 {
  191. compatible = "ti,am654-cpsw-phy-sel";
  192. reg= <0x0 0x40f04040 0x0 0x4>;
  193. reg-names = "gmii-sel";
  194. };
  195. };
  196. &main_mmc1_pins_default {
  197. u-boot,dm-spl;
  198. };
  199. &wkup_i2c0_pins_default {
  200. u-boot,dm-spl;
  201. };
  202. &wkup_i2c0 {
  203. u-boot,dm-spl;
  204. };
  205. &main_i2c0 {
  206. u-boot,dm-spl;
  207. };
  208. &main_i2c0_pins_default {
  209. u-boot,dm-spl;
  210. };
  211. &exp2 {
  212. u-boot,dm-spl;
  213. };
  214. &mcu_fss0_ospi0_pins_default {
  215. u-boot,dm-spl;
  216. };
  217. &fss {
  218. u-boot,dm-spl;
  219. };
  220. &ospi0 {
  221. u-boot,dm-spl;
  222. flash@0 {
  223. u-boot,dm-spl;
  224. };
  225. };
  226. &ospi1 {
  227. u-boot,dm-spl;
  228. flash@0 {
  229. u-boot,dm-spl;
  230. };
  231. };
  232. &mcu_fss0_ospi1_pins_default {
  233. u-boot,dm-spl;
  234. };