k3-am654-base-board-u-boot.dtsi 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  4. */
  5. #include <dt-bindings/pinctrl/k3.h>
  6. #include <dt-bindings/net/ti-dp83867.h>
  7. / {
  8. chosen {
  9. stdout-path = "serial2:115200n8";
  10. };
  11. aliases {
  12. serial2 = &main_uart0;
  13. ethernet0 = &cpsw_port1;
  14. };
  15. };
  16. &cbass_main{
  17. u-boot,dm-spl;
  18. sdhci1: sdhci@04FA0000 {
  19. compatible = "ti,am654-sdhci-5.1";
  20. reg = <0x0 0x4FA0000 0x0 0x1000>,
  21. <0x0 0x4FB0000 0x0 0x400>;
  22. clocks =<&k3_clks 48 0>, <&k3_clks 48 1>;
  23. clock-names = "clk_ahb", "clk_xin";
  24. power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
  25. max-frequency = <25000000>;
  26. ti,otap-del-sel-legacy = <0x0>;
  27. ti,otap-del-sel-mmc-hs = <0x0>;
  28. ti,otap-del-sel-sd-hs = <0x0>;
  29. ti,otap-del-sel-sdr12 = <0x0>;
  30. ti,otap-del-sel-sdr25 = <0x0>;
  31. ti,otap-del-sel-sdr50 = <0x8>;
  32. ti,otap-del-sel-sdr104 = <0x7>;
  33. ti,otap-del-sel-ddr50 = <0x4>;
  34. ti,otap-del-sel-ddr52 = <0x4>;
  35. ti,otap-del-sel-hs200 = <0x7>;
  36. ti,trm-icp = <0x8>;
  37. };
  38. };
  39. &cbass_mcu {
  40. u-boot,dm-spl;
  41. mcu_navss {
  42. u-boot,dm-spl;
  43. ringacc@2b800000 {
  44. u-boot,dm-spl;
  45. };
  46. dma-controller@285c0000 {
  47. u-boot,dm-spl;
  48. };
  49. };
  50. mcu_conf: scm_conf@40f00000 {
  51. compatible = "syscon";
  52. reg = <0x0 0x40f00000 0x0 0x20000>;
  53. };
  54. mcu_cpsw: cpsw_nuss@046000000 {
  55. compatible = "ti,am654-cpsw-nuss";
  56. #address-cells = <2>;
  57. #size-cells = <2>;
  58. reg = <0x0 0x46000000 0x0 0x200000>;
  59. reg-names = "cpsw_nuss";
  60. ranges;
  61. dma-coherent;
  62. clocks = <&k3_clks 5 10>;
  63. clock-names = "fck";
  64. power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
  65. dmas = <&mcu_udmap 0xf000>,
  66. <&mcu_udmap 0xf001>,
  67. <&mcu_udmap 0xf002>,
  68. <&mcu_udmap 0xf003>,
  69. <&mcu_udmap 0xf004>,
  70. <&mcu_udmap 0xf005>,
  71. <&mcu_udmap 0xf006>,
  72. <&mcu_udmap 0xf007>,
  73. <&mcu_udmap 0x7000>;
  74. dma-names = "tx0", "tx1", "tx2", "tx3",
  75. "tx4", "tx5", "tx6", "tx7",
  76. "rx";
  77. ports {
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. host: host@0 {
  81. reg = <0>;
  82. ti,label = "host";
  83. };
  84. cpsw_port1: port@1 {
  85. reg = <1>;
  86. ti,mac-only;
  87. ti,label = "port1";
  88. ti,syscon-efuse = <&mcu_conf 0x200>;
  89. };
  90. };
  91. davinci_mdio: mdio {
  92. #address-cells = <1>;
  93. #size-cells = <0>;
  94. bus_freq = <1000000>;
  95. };
  96. };
  97. };
  98. &cbass_wakeup {
  99. u-boot,dm-spl;
  100. };
  101. &secure_proxy_main {
  102. u-boot,dm-spl;
  103. };
  104. &dmsc {
  105. u-boot,dm-spl;
  106. k3_sysreset: sysreset-controller {
  107. compatible = "ti,sci-sysreset";
  108. u-boot,dm-spl;
  109. };
  110. };
  111. &k3_pds {
  112. u-boot,dm-spl;
  113. };
  114. &k3_clks {
  115. u-boot,dm-spl;
  116. };
  117. &k3_reset {
  118. u-boot,dm-spl;
  119. };
  120. &wkup_pmx0 {
  121. u-boot,dm-spl;
  122. wkup_i2c0_pins_default {
  123. u-boot,dm-spl;
  124. };
  125. };
  126. &main_pmx0 {
  127. u-boot,dm-spl;
  128. main_uart0_pins_default: main_uart0_pins_default {
  129. pinctrl-single,pins = <
  130. AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
  131. AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
  132. AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
  133. AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
  134. >;
  135. u-boot,dm-spl;
  136. };
  137. main_mmc0_pins_default: main_mmc0_pins_default {
  138. pinctrl-single,pins = <
  139. AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
  140. AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
  141. AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
  142. AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
  143. AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
  144. AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
  145. AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
  146. AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
  147. AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
  148. AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
  149. AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
  150. AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
  151. >;
  152. u-boot,dm-spl;
  153. };
  154. main_mmc1_pins_default: main_mmc1_pins_default {
  155. pinctrl-single,pins = <
  156. AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
  157. AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
  158. AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
  159. AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
  160. AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
  161. AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
  162. AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
  163. AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
  164. >;
  165. u-boot,dm-spl;
  166. };
  167. };
  168. &main_pmx1 {
  169. u-boot,dm-spl;
  170. };
  171. &wkup_pmx0 {
  172. mcu_cpsw_pins_default: mcu_cpsw_pins_default {
  173. pinctrl-single,pins = <
  174. AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
  175. AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
  176. AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
  177. AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
  178. AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
  179. AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
  180. AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
  181. AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
  182. AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
  183. AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
  184. AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
  185. AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
  186. >;
  187. };
  188. mcu_mdio_pins_default: mcu_mdio1_pins_default {
  189. pinctrl-single,pins = <
  190. AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
  191. AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
  192. >;
  193. };
  194. mcu-fss0-ospi0-pins-default {
  195. u-boot,dm-spl;
  196. };
  197. };
  198. &main_uart0 {
  199. u-boot,dm-spl;
  200. pinctrl-names = "default";
  201. pinctrl-0 = <&main_uart0_pins_default>;
  202. status = "okay";
  203. };
  204. &sdhci0 {
  205. u-boot,dm-spl;
  206. };
  207. &sdhci1 {
  208. u-boot,dm-spl;
  209. status = "okay";
  210. pinctrl-names = "default";
  211. pinctrl-0 = <&main_mmc1_pins_default>;
  212. sdhci-caps-mask = <0x7 0x0>;
  213. ti,driver-strength-ohm = <50>;
  214. };
  215. &mcu_cpsw {
  216. pinctrl-names = "default";
  217. pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
  218. };
  219. &davinci_mdio {
  220. phy0: ethernet-phy@0 {
  221. reg = <0>;
  222. /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
  223. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  224. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  225. };
  226. };
  227. &cpsw_port1 {
  228. phy-mode = "rgmii-rxid";
  229. phy-handle = <&phy0>;
  230. };
  231. &mcu_cpsw {
  232. reg = <0x0 0x46000000 0x0 0x200000>,
  233. <0x0 0x40f00200 0x0 0x2>;
  234. reg-names = "cpsw_nuss", "mac_efuse";
  235. cpsw-phy-sel@40f04040 {
  236. compatible = "ti,am654-cpsw-phy-sel";
  237. reg= <0x0 0x40f04040 0x0 0x4>;
  238. reg-names = "gmii-sel";
  239. };
  240. };
  241. &wkup_i2c0 {
  242. u-boot,dm-spl;
  243. };
  244. &usb1 {
  245. dr_mode = "peripheral";
  246. };
  247. &fss {
  248. u-boot,dm-spl;
  249. };
  250. &ospi0 {
  251. u-boot,dm-spl;
  252. flash@0{
  253. u-boot,dm-spl;
  254. };
  255. };