k3-am65-mcu.dtsi 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for AM6 SoC Family MCU Domain peripherals
  4. *
  5. * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
  6. */
  7. &cbass_mcu {
  8. mcu_uart0: serial@40a00000 {
  9. compatible = "ti,am654-uart";
  10. reg = <0x00 0x40a00000 0x00 0x100>;
  11. reg-shift = <2>;
  12. reg-io-width = <4>;
  13. interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
  14. clock-frequency = <96000000>;
  15. current-speed = <115200>;
  16. };
  17. mcu_i2c0: i2c@40b00000 {
  18. compatible = "ti,am654-i2c", "ti,omap4-i2c";
  19. reg = <0x0 0x40b00000 0x0 0x100>;
  20. interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
  21. #address-cells = <1>;
  22. #size-cells = <0>;
  23. clock-names = "fck";
  24. clocks = <&k3_clks 114 1>;
  25. power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
  26. };
  27. mcu_r5fss0: r5fss@41000000 {
  28. compatible = "ti,am654-r5fss";
  29. lockstep-mode = <0>;
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. ranges = <0x41000000 0x00 0x41000000 0x20000>,
  33. <0x41400000 0x00 0x41400000 0x20000>;
  34. power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
  35. mcu_r5fss0_core0: r5f@41000000 {
  36. compatible = "ti,am654-r5f";
  37. reg = <0x41000000 0x00008000>,
  38. <0x41010000 0x00008000>;
  39. reg-names = "atcm", "btcm";
  40. ti,sci = <&dmsc>;
  41. ti,sci-dev-id = <159>;
  42. ti,sci-proc-ids = <0x01 0xFF>;
  43. resets = <&k3_reset 159 1>;
  44. atcm-enable = <1>;
  45. btcm-enable = <1>;
  46. loczrama = <1>;
  47. };
  48. mcu_r5fss0_core1: r5f@41400000 {
  49. compatible = "ti,am654-r5f";
  50. reg = <0x41400000 0x00008000>,
  51. <0x41410000 0x00008000>;
  52. reg-names = "atcm", "btcm";
  53. ti,sci = <&dmsc>;
  54. ti,sci-dev-id = <245>;
  55. ti,sci-proc-ids = <0x02 0xFF>;
  56. resets = <&k3_reset 245 1>;
  57. atcm-enable = <1>;
  58. btcm-enable = <1>;
  59. loczrama = <1>;
  60. };
  61. };
  62. fss: fss@47000000 {
  63. compatible = "simple-bus";
  64. #address-cells = <2>;
  65. #size-cells = <2>;
  66. ranges;
  67. ospi0: spi@47040000 {
  68. compatible = "ti,am654-ospi", "cdns,qspi-nor";
  69. reg = <0x0 0x47040000 0x0 0x100>,
  70. <0x5 0x00000000 0x1 0x0000000>;
  71. interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
  72. cdns,fifo-depth = <256>;
  73. cdns,fifo-width = <4>;
  74. cdns,trigger-address = <0x0>;
  75. clocks = <&k3_clks 248 0>;
  76. assigned-clocks = <&k3_clks 248 0>;
  77. assigned-clock-parents = <&k3_clks 248 2>;
  78. assigned-clock-rates = <166666666>;
  79. power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
  80. #address-cells = <1>;
  81. #size-cells = <0>;
  82. };
  83. ospi1: spi@47050000 {
  84. compatible = "ti,am654-ospi", "cdns,qspi-nor";
  85. reg = <0x0 0x47050000 0x0 0x100>,
  86. <0x7 0x00000000 0x1 0x00000000>;
  87. interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
  88. cdns,fifo-depth = <256>;
  89. cdns,fifo-width = <4>;
  90. cdns,trigger-address = <0x0>;
  91. clocks = <&k3_clks 249 6>;
  92. power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
  93. #address-cells = <1>;
  94. #size-cells = <0>;
  95. };
  96. };
  97. mcu_navss {
  98. compatible = "simple-mfd";
  99. #address-cells = <2>;
  100. #size-cells = <2>;
  101. ranges;
  102. dma-coherent;
  103. dma-ranges;
  104. ti,sci-dev-id = <119>;
  105. mcu_ringacc: ringacc@2b800000 {
  106. compatible = "ti,am654-navss-ringacc";
  107. reg = <0x0 0x2b800000 0x0 0x400000>,
  108. <0x0 0x2b000000 0x0 0x400000>,
  109. <0x0 0x28590000 0x0 0x100>,
  110. <0x0 0x2a500000 0x0 0x40000>;
  111. reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
  112. ti,num-rings = <286>;
  113. ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
  114. ti,dma-ring-reset-quirk;
  115. ti,sci = <&dmsc>;
  116. ti,sci-dev-id = <195>;
  117. };
  118. mcu_udmap: dma-controller@285c0000 {
  119. compatible = "ti,am654-navss-mcu-udmap";
  120. reg = <0x0 0x285c0000 0x0 0x100>,
  121. <0x0 0x2a800000 0x0 0x40000>,
  122. <0x0 0x2aa00000 0x0 0x40000>;
  123. reg-names = "gcfg", "rchanrt", "tchanrt";
  124. #dma-cells = <1>;
  125. ti,sci = <&dmsc>;
  126. ti,sci-dev-id = <194>;
  127. ti,ringacc = <&mcu_ringacc>;
  128. ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
  129. <0x2>; /* TX_CHAN */
  130. ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
  131. <0x4>; /* RX_CHAN */
  132. ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
  133. };
  134. };
  135. };