fu540_ddr.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * (C) Copyright 2020 SiFive, Inc.
  4. *
  5. * Authors:
  6. * Pragnesh Patel <pragnesh.patel@sifive.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <init.h>
  12. #include <ram.h>
  13. #include <syscon.h>
  14. #include <asm/io.h>
  15. #include <clk.h>
  16. #include <wait_bit.h>
  17. #include <linux/bitops.h>
  18. #define DENALI_CTL_0 0
  19. #define DENALI_CTL_21 21
  20. #define DENALI_CTL_120 120
  21. #define DENALI_CTL_132 132
  22. #define DENALI_CTL_136 136
  23. #define DENALI_CTL_170 170
  24. #define DENALI_CTL_181 181
  25. #define DENALI_CTL_182 182
  26. #define DENALI_CTL_184 184
  27. #define DENALI_CTL_208 208
  28. #define DENALI_CTL_209 209
  29. #define DENALI_CTL_210 210
  30. #define DENALI_CTL_212 212
  31. #define DENALI_CTL_214 214
  32. #define DENALI_CTL_216 216
  33. #define DENALI_CTL_224 224
  34. #define DENALI_CTL_225 225
  35. #define DENALI_CTL_260 260
  36. #define DENALI_PHY_1152 1152
  37. #define DENALI_PHY_1214 1214
  38. #define DRAM_CLASS_OFFSET 8
  39. #define DRAM_CLASS_DDR4 0xA
  40. #define OPTIMAL_RMODW_EN_OFFSET 0
  41. #define DISABLE_RD_INTERLEAVE_OFFSET 16
  42. #define OUT_OF_RANGE_OFFSET 1
  43. #define MULTIPLE_OUT_OF_RANGE_OFFSET 2
  44. #define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
  45. #define MC_INIT_COMPLETE_OFFSET 8
  46. #define LEVELING_OPERATION_COMPLETED_OFFSET 22
  47. #define DFI_PHY_WRLELV_MODE_OFFSET 24
  48. #define DFI_PHY_RDLVL_MODE_OFFSET 24
  49. #define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
  50. #define VREF_EN_OFFSET 24
  51. #define PORT_ADDR_PROTECTION_EN_OFFSET 0
  52. #define AXI0_ADDRESS_RANGE_ENABLE 8
  53. #define AXI0_RANGE_PROT_BITS_0_OFFSET 24
  54. #define RDLVL_EN_OFFSET 16
  55. #define RDLVL_GATE_EN_OFFSET 24
  56. #define WRLVL_EN_OFFSET 0
  57. #define PHY_RX_CAL_DQ0_0_OFFSET 0
  58. #define PHY_RX_CAL_DQ1_0_OFFSET 16
  59. DECLARE_GLOBAL_DATA_PTR;
  60. struct fu540_ddrctl {
  61. volatile u32 denali_ctl[265];
  62. };
  63. struct fu540_ddrphy {
  64. volatile u32 denali_phy[1215];
  65. };
  66. /**
  67. * struct fu540_ddr_info
  68. *
  69. * @dev : pointer for the device
  70. * @info : UCLASS RAM information
  71. * @ctl : DDR controller base address
  72. * @phy : DDR PHY base address
  73. * @ctrl : DDR control base address
  74. * @physical_filter_ctrl : DDR physical filter control base address
  75. */
  76. struct fu540_ddr_info {
  77. struct udevice *dev;
  78. struct ram_info info;
  79. struct fu540_ddrctl *ctl;
  80. struct fu540_ddrphy *phy;
  81. struct clk ddr_clk;
  82. u32 *physical_filter_ctrl;
  83. };
  84. #if defined(CONFIG_SPL_BUILD)
  85. struct fu540_ddr_params {
  86. struct fu540_ddrctl pctl_regs;
  87. struct fu540_ddrphy phy_regs;
  88. };
  89. struct sifive_dmc_plat {
  90. struct fu540_ddr_params ddr_params;
  91. };
  92. /*
  93. * TODO : It can be possible to use common sdram_copy_to_reg() API
  94. * n: Unit bytes
  95. */
  96. static void sdram_copy_to_reg(volatile u32 *dest,
  97. volatile u32 *src, u32 n)
  98. {
  99. int i;
  100. for (i = 0; i < n / sizeof(u32); i++) {
  101. writel(*src, dest);
  102. src++;
  103. dest++;
  104. }
  105. }
  106. static void fu540_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr)
  107. {
  108. u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
  109. writel(0x0, DENALI_CTL_209 + ctl);
  110. writel(end_addr_16kblocks, DENALI_CTL_210 + ctl);
  111. writel(0x0, DENALI_CTL_212 + ctl);
  112. writel(0x0, DENALI_CTL_214 + ctl);
  113. writel(0x0, DENALI_CTL_216 + ctl);
  114. setbits_le32(DENALI_CTL_224 + ctl,
  115. 0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
  116. writel(0xFFFFFFFF, DENALI_CTL_225 + ctl);
  117. setbits_le32(DENALI_CTL_208 + ctl, 0x1 << AXI0_ADDRESS_RANGE_ENABLE);
  118. setbits_le32(DENALI_CTL_208 + ctl,
  119. 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET);
  120. }
  121. static void fu540_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
  122. u64 ddr_end)
  123. {
  124. volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
  125. setbits_le32(DENALI_CTL_0 + ctl, 0x1);
  126. wait_for_bit_le32((void *)ctl + DENALI_CTL_132,
  127. BIT(MC_INIT_COMPLETE_OFFSET), false, 100, false);
  128. /* Disable the BusBlocker in front of the controller AXI slave ports */
  129. filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2);
  130. }
  131. static void fu540_ddr_check_errata(u32 regbase, u32 updownreg)
  132. {
  133. u64 fails = 0;
  134. u32 dq = 0;
  135. u32 down, up;
  136. u8 failc0, failc1;
  137. u32 phy_rx_cal_dqn_0_offset;
  138. for (u32 bit = 0; bit < 2; bit++) {
  139. if (bit == 0) {
  140. phy_rx_cal_dqn_0_offset =
  141. PHY_RX_CAL_DQ0_0_OFFSET;
  142. } else {
  143. phy_rx_cal_dqn_0_offset =
  144. PHY_RX_CAL_DQ1_0_OFFSET;
  145. }
  146. down = (updownreg >>
  147. phy_rx_cal_dqn_0_offset) & 0x3F;
  148. up = (updownreg >>
  149. (phy_rx_cal_dqn_0_offset + 6)) &
  150. 0x3F;
  151. failc0 = ((down == 0) && (up == 0x3F));
  152. failc1 = ((up == 0) && (down == 0x3F));
  153. /* print error message on failure */
  154. if (failc0 || failc1) {
  155. if (fails == 0)
  156. printf("DDR error in fixing up\n");
  157. fails |= (1 << dq);
  158. char slicelsc = '0';
  159. char slicemsc = '0';
  160. slicelsc += (dq % 10);
  161. slicemsc += (dq / 10);
  162. printf("S ");
  163. printf("%c", slicemsc);
  164. printf("%c", slicelsc);
  165. if (failc0)
  166. printf("U");
  167. else
  168. printf("D");
  169. printf("\n");
  170. }
  171. dq++;
  172. }
  173. }
  174. static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg)
  175. {
  176. u32 slicebase = 0;
  177. /* check errata condition */
  178. for (u32 slice = 0; slice < 8; slice++) {
  179. u32 regbase = slicebase + 34;
  180. for (u32 reg = 0; reg < 4; reg++) {
  181. u32 updownreg = readl(regbase + reg + ddrphyreg);
  182. fu540_ddr_check_errata(regbase, updownreg);
  183. }
  184. slicebase += 128;
  185. }
  186. return(0);
  187. }
  188. static u32 fu540_ddr_get_dram_class(volatile u32 *ctl)
  189. {
  190. u32 reg = readl(DENALI_CTL_0 + ctl);
  191. return ((reg >> DRAM_CLASS_OFFSET) & 0xF);
  192. }
  193. static int fu540_ddr_setup(struct udevice *dev)
  194. {
  195. struct fu540_ddr_info *priv = dev_get_priv(dev);
  196. struct sifive_dmc_plat *plat = dev_get_platdata(dev);
  197. struct fu540_ddr_params *params = &plat->ddr_params;
  198. volatile u32 *denali_ctl = priv->ctl->denali_ctl;
  199. volatile u32 *denali_phy = priv->phy->denali_phy;
  200. const u64 ddr_size = priv->info.size;
  201. const u64 ddr_end = priv->info.base + ddr_size;
  202. int ret, i;
  203. u32 physet;
  204. ret = dev_read_u32_array(dev, "sifive,ddr-params",
  205. (u32 *)&plat->ddr_params,
  206. sizeof(plat->ddr_params) / sizeof(u32));
  207. if (ret) {
  208. printf("%s: Cannot read sifive,ddr-params %d\n",
  209. __func__, ret);
  210. return ret;
  211. }
  212. sdram_copy_to_reg(priv->ctl->denali_ctl,
  213. params->pctl_regs.denali_ctl,
  214. sizeof(struct fu540_ddrctl));
  215. /* phy reset */
  216. for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) {
  217. physet = params->phy_regs.denali_phy[i];
  218. priv->phy->denali_phy[i] = physet;
  219. }
  220. for (i = 0; i < DENALI_PHY_1152; i++) {
  221. physet = params->phy_regs.denali_phy[i];
  222. priv->phy->denali_phy[i] = physet;
  223. }
  224. /* Disable read interleave DENALI_CTL_120 */
  225. setbits_le32(DENALI_CTL_120 + denali_ctl,
  226. 1 << DISABLE_RD_INTERLEAVE_OFFSET);
  227. /* Disable optimal read/modify/write logic DENALI_CTL_21 */
  228. clrbits_le32(DENALI_CTL_21 + denali_ctl, 1 << OPTIMAL_RMODW_EN_OFFSET);
  229. /* Enable write Leveling DENALI_CTL_170 */
  230. setbits_le32(DENALI_CTL_170 + denali_ctl, (1 << WRLVL_EN_OFFSET)
  231. | (1 << DFI_PHY_WRLELV_MODE_OFFSET));
  232. /* Enable read leveling DENALI_CTL_181 and DENALI_CTL_260 */
  233. setbits_le32(DENALI_CTL_181 + denali_ctl,
  234. 1 << DFI_PHY_RDLVL_MODE_OFFSET);
  235. setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_EN_OFFSET);
  236. /* Enable read leveling gate DENALI_CTL_260 and DENALI_CTL_182 */
  237. setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_GATE_EN_OFFSET);
  238. setbits_le32(DENALI_CTL_182 + denali_ctl,
  239. 1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET);
  240. if (fu540_ddr_get_dram_class(denali_ctl) == DRAM_CLASS_DDR4) {
  241. /* Enable vref training DENALI_CTL_184 */
  242. setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET);
  243. }
  244. /* Mask off leveling completion interrupt DENALI_CTL_136 */
  245. setbits_le32(DENALI_CTL_136 + denali_ctl,
  246. 1 << LEVELING_OPERATION_COMPLETED_OFFSET);
  247. /* Mask off MC init complete interrupt DENALI_CTL_136 */
  248. setbits_le32(DENALI_CTL_136 + denali_ctl, 1 << MC_INIT_COMPLETE_OFFSET);
  249. /* Mask off out of range interrupts DENALI_CTL_136 */
  250. setbits_le32(DENALI_CTL_136 + denali_ctl, (1 << OUT_OF_RANGE_OFFSET)
  251. | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
  252. /* set up range protection */
  253. fu540_ddr_setup_range_protection(denali_ctl, priv->info.size);
  254. /* Mask off port command error interrupt DENALI_CTL_136 */
  255. setbits_le32(DENALI_CTL_136 + denali_ctl,
  256. 1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET);
  257. fu540_ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end);
  258. fu540_ddr_phy_fixup(denali_phy);
  259. /* check size */
  260. priv->info.size = get_ram_size((long *)priv->info.base,
  261. ddr_size);
  262. debug("%s : %lx\n", __func__, (uintptr_t)priv->info.size);
  263. /* check memory access for all memory */
  264. if (priv->info.size != ddr_size) {
  265. printf("DDR invalid size : 0x%lx, expected 0x%lx\n",
  266. (uintptr_t)priv->info.size, (uintptr_t)ddr_size);
  267. return -EINVAL;
  268. }
  269. return 0;
  270. }
  271. #endif
  272. static int fu540_ddr_probe(struct udevice *dev)
  273. {
  274. struct fu540_ddr_info *priv = dev_get_priv(dev);
  275. /* Read memory base and size from DT */
  276. fdtdec_setup_mem_size_base();
  277. priv->info.base = gd->ram_base;
  278. priv->info.size = gd->ram_size;
  279. #if defined(CONFIG_SPL_BUILD)
  280. int ret;
  281. u32 clock = 0;
  282. debug("FU540 DDR probe\n");
  283. priv->dev = dev;
  284. ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
  285. if (ret) {
  286. debug("clk get failed %d\n", ret);
  287. return ret;
  288. }
  289. ret = dev_read_u32(dev, "clock-frequency", &clock);
  290. if (ret) {
  291. debug("clock-frequency not found in dt %d\n", ret);
  292. return ret;
  293. } else {
  294. ret = clk_set_rate(&priv->ddr_clk, clock);
  295. if (ret < 0) {
  296. debug("Could not set DDR clock\n");
  297. return ret;
  298. }
  299. }
  300. ret = clk_enable(&priv->ddr_clk);
  301. if (ret < 0) {
  302. debug("Could not enable DDR clock\n");
  303. return ret;
  304. }
  305. priv->ctl = (struct fu540_ddrctl *)dev_read_addr_index(dev, 0);
  306. priv->phy = (struct fu540_ddrphy *)dev_read_addr_index(dev, 1);
  307. priv->physical_filter_ctrl = (u32 *)dev_read_addr_index(dev, 2);
  308. return fu540_ddr_setup(dev);
  309. #endif
  310. return 0;
  311. }
  312. static int fu540_ddr_get_info(struct udevice *dev, struct ram_info *info)
  313. {
  314. struct fu540_ddr_info *priv = dev_get_priv(dev);
  315. *info = priv->info;
  316. return 0;
  317. }
  318. static struct ram_ops fu540_ddr_ops = {
  319. .get_info = fu540_ddr_get_info,
  320. };
  321. static const struct udevice_id fu540_ddr_ids[] = {
  322. { .compatible = "sifive,fu540-c000-ddr" },
  323. { }
  324. };
  325. U_BOOT_DRIVER(fu540_ddr) = {
  326. .name = "fu540_ddr",
  327. .id = UCLASS_RAM,
  328. .of_match = fu540_ddr_ids,
  329. .ops = &fu540_ddr_ops,
  330. .probe = fu540_ddr_probe,
  331. .priv_auto_alloc_size = sizeof(struct fu540_ddr_info),
  332. #if defined(CONFIG_SPL_BUILD)
  333. .platdata_auto_alloc_size = sizeof(struct sifive_dmc_plat),
  334. #endif
  335. };