socrates.c 10 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  4. *
  5. * Copyright 2004 Freescale Semiconductor.
  6. * (C) Copyright 2002,2003, Motorola Inc.
  7. * Xianghua Xiao, (X.Xiao@motorola.com)
  8. *
  9. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  10. *
  11. * SPDX-License-Identifier: GPL-2.0+
  12. */
  13. #include <common.h>
  14. #include <pci.h>
  15. #include <asm/processor.h>
  16. #include <asm/immap_85xx.h>
  17. #include <ioports.h>
  18. #include <flash.h>
  19. #include <libfdt.h>
  20. #include <fdt_support.h>
  21. #include <asm/io.h>
  22. #include <i2c.h>
  23. #include <mb862xx.h>
  24. #include <video_fb.h>
  25. #include "upm_table.h"
  26. DECLARE_GLOBAL_DATA_PTR;
  27. extern flash_info_t flash_info[]; /* FLASH chips info */
  28. extern GraphicDevice mb862xx;
  29. void local_bus_init (void);
  30. ulong flash_get_size (ulong base, int banknum);
  31. int checkboard (void)
  32. {
  33. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  34. char buf[64];
  35. int f;
  36. int i = getenv_f("serial#", buf, sizeof(buf));
  37. #ifdef CONFIG_PCI
  38. char *src;
  39. #endif
  40. puts("Board: Socrates");
  41. if (i > 0) {
  42. puts(", serial# ");
  43. puts(buf);
  44. }
  45. putc('\n');
  46. #ifdef CONFIG_PCI
  47. /* Check the PCI_clk sel bit */
  48. if (in_be32(&gur->porpllsr) & (1<<15)) {
  49. src = "SYSCLK";
  50. f = CONFIG_SYS_CLK_FREQ;
  51. } else {
  52. src = "PCI_CLK";
  53. f = CONFIG_PCI_CLK_FREQ;
  54. }
  55. printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
  56. #else
  57. printf ("PCI1: disabled\n");
  58. #endif
  59. /*
  60. * Initialize local bus.
  61. */
  62. local_bus_init ();
  63. return 0;
  64. }
  65. int misc_init_r (void)
  66. {
  67. /*
  68. * Adjust flash start and offset to detected values
  69. */
  70. gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  71. gd->bd->bi_flashoffset = 0;
  72. /*
  73. * Check if boot FLASH isn't max size
  74. */
  75. if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
  76. set_lbc_or(0, gd->bd->bi_flashstart |
  77. (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
  78. set_lbc_br(0, gd->bd->bi_flashstart |
  79. (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
  80. /*
  81. * Re-check to get correct base address
  82. */
  83. flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
  84. }
  85. /*
  86. * Check if only one FLASH bank is available
  87. */
  88. if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
  89. set_lbc_or(1, 0);
  90. set_lbc_br(1, 0);
  91. /*
  92. * Re-do flash protection upon new addresses
  93. */
  94. flash_protect (FLAG_PROTECT_CLEAR,
  95. gd->bd->bi_flashstart, 0xffffffff,
  96. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  97. /* Monitor protection ON by default */
  98. flash_protect (FLAG_PROTECT_SET,
  99. CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
  100. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  101. /* Environment protection ON by default */
  102. flash_protect (FLAG_PROTECT_SET,
  103. CONFIG_ENV_ADDR,
  104. CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
  105. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  106. /* Redundant environment protection ON by default */
  107. flash_protect (FLAG_PROTECT_SET,
  108. CONFIG_ENV_ADDR_REDUND,
  109. CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
  110. &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
  111. }
  112. return 0;
  113. }
  114. /*
  115. * Initialize Local Bus
  116. */
  117. void local_bus_init (void)
  118. {
  119. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  120. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  121. sys_info_t sysinfo;
  122. uint clkdiv;
  123. uint lbc_mhz;
  124. uint lcrr = CONFIG_SYS_LBC_LCRR;
  125. get_sys_info (&sysinfo);
  126. clkdiv = lbc->lcrr & LCRR_CLKDIV;
  127. lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
  128. /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
  129. if (lbc_mhz >= 66)
  130. lcrr &= ~LCRR_DBYP; /* DLL Enabled */
  131. else
  132. lcrr |= LCRR_DBYP; /* DLL Bypass */
  133. out_be32 (&lbc->lcrr, lcrr);
  134. asm ("sync;isync;msync");
  135. out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
  136. out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
  137. out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
  138. out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
  139. /* Init UPMA for FPGA access */
  140. out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
  141. upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
  142. /* Init UPMB for Lime controller access */
  143. out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
  144. upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
  145. }
  146. #if defined(CONFIG_PCI)
  147. /*
  148. * Initialize PCI Devices, report devices found.
  149. */
  150. #ifndef CONFIG_PCI_PNP
  151. static struct pci_config_table pci_mpc85xxads_config_table[] = {
  152. {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  153. PCI_IDSEL_NUMBER, PCI_ANY_ID,
  154. pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
  155. PCI_ENET0_MEMADDR,
  156. PCI_COMMAND_MEMORY |
  157. PCI_COMMAND_MASTER}},
  158. {}
  159. };
  160. #endif
  161. static struct pci_controller hose = {
  162. #ifndef CONFIG_PCI_PNP
  163. config_table:pci_mpc85xxads_config_table,
  164. #endif
  165. };
  166. #endif /* CONFIG_PCI */
  167. void pci_init_board (void)
  168. {
  169. #ifdef CONFIG_PCI
  170. pci_mpc85xx_init (&hose);
  171. #endif /* CONFIG_PCI */
  172. }
  173. #ifdef CONFIG_BOARD_EARLY_INIT_R
  174. int board_early_init_r (void)
  175. {
  176. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  177. /* set and reset the GPIO pin 2 which will reset the W83782G chip */
  178. out_8((unsigned char*)&gur->gpoutdr, 0x3F );
  179. out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
  180. udelay(200);
  181. out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
  182. return (0);
  183. }
  184. #endif /* CONFIG_BOARD_EARLY_INIT_R */
  185. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  186. void
  187. ft_board_setup(void *blob, bd_t *bd)
  188. {
  189. u32 val[12];
  190. int rc, i = 0;
  191. ft_cpu_setup(blob, bd);
  192. /* Fixup NOR FLASH mapping */
  193. val[i++] = 0; /* chip select number */
  194. val[i++] = 0; /* always 0 */
  195. val[i++] = gd->bd->bi_flashstart;
  196. val[i++] = gd->bd->bi_flashsize;
  197. if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
  198. /* Fixup LIME mapping */
  199. val[i++] = 2; /* chip select number */
  200. val[i++] = 0; /* always 0 */
  201. val[i++] = CONFIG_SYS_LIME_BASE;
  202. val[i++] = CONFIG_SYS_LIME_SIZE;
  203. }
  204. /* Fixup FPGA mapping */
  205. val[i++] = 3; /* chip select number */
  206. val[i++] = 0; /* always 0 */
  207. val[i++] = CONFIG_SYS_FPGA_BASE;
  208. val[i++] = CONFIG_SYS_FPGA_SIZE;
  209. rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
  210. val, i * sizeof(u32), 1);
  211. if (rc)
  212. printf("Unable to update localbus ranges, err=%s\n",
  213. fdt_strerror(rc));
  214. }
  215. #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
  216. #define DEFAULT_BRIGHTNESS 25
  217. #define BACKLIGHT_ENABLE (1 << 31)
  218. static const gdc_regs init_regs [] =
  219. {
  220. {0x0100, 0x00010f00},
  221. {0x0020, 0x801901df},
  222. {0x0024, 0x00000000},
  223. {0x0028, 0x00000000},
  224. {0x002c, 0x00000000},
  225. {0x0110, 0x00000000},
  226. {0x0114, 0x00000000},
  227. {0x0118, 0x01df0320},
  228. {0x0004, 0x041f0000},
  229. {0x0008, 0x031f031f},
  230. {0x000c, 0x017f0349},
  231. {0x0010, 0x020c0000},
  232. {0x0014, 0x01df01e9},
  233. {0x0018, 0x00000000},
  234. {0x001c, 0x01e00320},
  235. {0x0100, 0x80010f00},
  236. {0x0, 0x0}
  237. };
  238. const gdc_regs *board_get_regs (void)
  239. {
  240. return init_regs;
  241. }
  242. int lime_probe(void)
  243. {
  244. uint cfg_br2;
  245. uint cfg_or2;
  246. int type;
  247. cfg_br2 = get_lbc_br(2);
  248. cfg_or2 = get_lbc_or(2);
  249. /* Configure GPCM for CS2 */
  250. set_lbc_br(2, 0);
  251. set_lbc_or(2, 0xfc000410);
  252. set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
  253. /* Get controller type */
  254. type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
  255. /* Restore previous CS2 configuration */
  256. set_lbc_br(2, 0);
  257. set_lbc_or(2, cfg_or2);
  258. set_lbc_br(2, cfg_br2);
  259. return (type == MB862XX_TYPE_LIME) ? 1 : 0;
  260. }
  261. /* Returns Lime base address */
  262. unsigned int board_video_init (void)
  263. {
  264. if (!lime_probe())
  265. return 0;
  266. mb862xx.winSizeX = 800;
  267. mb862xx.winSizeY = 480;
  268. mb862xx.gdfIndex = GDF_15BIT_555RGB;
  269. mb862xx.gdfBytesPP = 2;
  270. return CONFIG_SYS_LIME_BASE;
  271. }
  272. #define W83782D_REG_CFG 0x40
  273. #define W83782D_REG_BANK_SEL 0x4e
  274. #define W83782D_REG_ADCCLK 0x4b
  275. #define W83782D_REG_BEEP_CTRL 0x4d
  276. #define W83782D_REG_BEEP_CTRL2 0x57
  277. #define W83782D_REG_PWMOUT1 0x5b
  278. #define W83782D_REG_VBAT 0x5d
  279. static int w83782d_hwmon_init(void)
  280. {
  281. u8 buf;
  282. if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
  283. return -1;
  284. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
  285. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
  286. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);
  287. buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
  288. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
  289. buf | 0x80);
  290. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
  291. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
  292. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);
  293. buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG);
  294. i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG,
  295. (buf & 0xf4) | 0x01);
  296. return 0;
  297. }
  298. static void board_backlight_brightness(int br)
  299. {
  300. u32 reg;
  301. u8 buf;
  302. u8 old_buf;
  303. /* Select bank 0 */
  304. if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
  305. goto err;
  306. else
  307. buf = old_buf & 0xf8;
  308. if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
  309. goto err;
  310. if (br > 0) {
  311. /* PWMOUT1 duty cycle ctrl */
  312. buf = 255 / (100 / br);
  313. if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
  314. goto err;
  315. /* LEDs on */
  316. reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
  317. if (!(reg & BACKLIGHT_ENABLE));
  318. out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c),
  319. reg | BACKLIGHT_ENABLE);
  320. } else {
  321. buf = 0;
  322. if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
  323. goto err;
  324. /* LEDs off */
  325. reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
  326. reg &= ~BACKLIGHT_ENABLE;
  327. out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg);
  328. }
  329. /* Restore previous bank setting */
  330. if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
  331. goto err;
  332. return;
  333. err:
  334. printf("W83782G I2C access failed\n");
  335. }
  336. void board_backlight_switch (int flag)
  337. {
  338. char * param;
  339. int rc;
  340. if (w83782d_hwmon_init())
  341. printf ("hwmon IC init failed\n");
  342. if (flag) {
  343. param = getenv("brightness");
  344. rc = param ? simple_strtol(param, NULL, 10) : -1;
  345. if (rc < 0)
  346. rc = DEFAULT_BRIGHTNESS;
  347. } else {
  348. rc = 0;
  349. }
  350. board_backlight_brightness(rc);
  351. }
  352. #if defined(CONFIG_CONSOLE_EXTRA_INFO)
  353. /*
  354. * Return text to be printed besides the logo.
  355. */
  356. void video_get_info_str (int line_number, char *info)
  357. {
  358. if (line_number == 1) {
  359. strcpy (info, " Board: Socrates");
  360. } else {
  361. info [0] = '\0';
  362. }
  363. }
  364. #endif