sbc8548.c 6.9 KB

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  1. /*
  2. * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
  3. *
  4. * Copyright 2007 Embedded Specialties, Inc.
  5. *
  6. * Copyright 2004, 2007 Freescale Semiconductor.
  7. *
  8. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. #include <common.h>
  13. #include <pci.h>
  14. #include <asm/processor.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/fsl_pci.h>
  17. #include <asm/fsl_ddr_sdram.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <spd_sdram.h>
  20. #include <netdev.h>
  21. #include <tsec.h>
  22. #include <miiphy.h>
  23. #include <libfdt.h>
  24. #include <fdt_support.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. void local_bus_init(void);
  27. int board_early_init_f (void)
  28. {
  29. return 0;
  30. }
  31. int checkboard (void)
  32. {
  33. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  34. volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
  35. printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
  36. in_8(rev) >> 4);
  37. /*
  38. * Initialize local bus.
  39. */
  40. local_bus_init ();
  41. out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
  42. out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
  43. return 0;
  44. }
  45. /*
  46. * Initialize Local Bus
  47. */
  48. void
  49. local_bus_init(void)
  50. {
  51. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  52. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  53. uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
  54. sys_info_t sysinfo;
  55. get_sys_info(&sysinfo);
  56. lbc_mhz = sysinfo.freq_localbus / 1000000;
  57. clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
  58. debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
  59. out_be32(&gur->lbiuiplldcr1, 0x00078080);
  60. if (clkdiv == 16) {
  61. out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
  62. } else if (clkdiv == 8) {
  63. out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
  64. } else if (clkdiv == 4) {
  65. out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
  66. }
  67. /*
  68. * Local Bus Clock > 83.3 MHz. According to timing
  69. * specifications set LCRR[EADC] to 2 delay cycles.
  70. */
  71. if (lbc_mhz > 83) {
  72. lcrr &= ~LCRR_EADC;
  73. lcrr |= LCRR_EADC_2;
  74. }
  75. /*
  76. * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
  77. * disable PLL bypass for Local Bus Clock > 83 MHz.
  78. */
  79. if (lbc_mhz >= 66)
  80. lcrr &= (~LCRR_DBYP); /* DLL Enabled */
  81. else
  82. lcrr |= LCRR_DBYP; /* DLL Bypass */
  83. out_be32(&lbc->lcrr, lcrr);
  84. asm("sync;isync;msync");
  85. /*
  86. * According to MPC8548ERMAD Rev.1.3 read back LCRR
  87. * and terminate with isync
  88. */
  89. lcrr = in_be32(&lbc->lcrr);
  90. asm ("isync;");
  91. /* let DLL stabilize */
  92. udelay(500);
  93. out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
  94. out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
  95. }
  96. /*
  97. * Initialize SDRAM memory on the Local Bus.
  98. */
  99. void lbc_sdram_init(void)
  100. {
  101. #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
  102. uint idx;
  103. const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
  104. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  105. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  106. uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
  107. puts(" SDRAM: ");
  108. print_size(size, "\n");
  109. /*
  110. * Setup SDRAM Base and Option Registers
  111. */
  112. set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
  113. set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
  114. set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
  115. set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
  116. out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
  117. asm("msync");
  118. out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
  119. out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
  120. asm("msync");
  121. /*
  122. * Issue PRECHARGE ALL command.
  123. */
  124. out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
  125. asm("sync;msync");
  126. *sdram_addr = 0xff;
  127. ppcDcbf((unsigned long) sdram_addr);
  128. *sdram_addr2 = 0xff;
  129. ppcDcbf((unsigned long) sdram_addr2);
  130. udelay(100);
  131. /*
  132. * Issue 8 AUTO REFRESH commands.
  133. */
  134. for (idx = 0; idx < 8; idx++) {
  135. out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
  136. asm("sync;msync");
  137. *sdram_addr = 0xff;
  138. ppcDcbf((unsigned long) sdram_addr);
  139. *sdram_addr2 = 0xff;
  140. ppcDcbf((unsigned long) sdram_addr2);
  141. udelay(100);
  142. }
  143. /*
  144. * Issue 8 MODE-set command.
  145. */
  146. out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
  147. asm("sync;msync");
  148. *sdram_addr = 0xff;
  149. ppcDcbf((unsigned long) sdram_addr);
  150. *sdram_addr2 = 0xff;
  151. ppcDcbf((unsigned long) sdram_addr2);
  152. udelay(100);
  153. /*
  154. * Issue RFEN command.
  155. */
  156. out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
  157. asm("sync;msync");
  158. *sdram_addr = 0xff;
  159. ppcDcbf((unsigned long) sdram_addr);
  160. *sdram_addr2 = 0xff;
  161. ppcDcbf((unsigned long) sdram_addr2);
  162. udelay(200); /* Overkill. Must wait > 200 bus cycles */
  163. #endif /* enable SDRAM init */
  164. }
  165. #if defined(CONFIG_SYS_DRAM_TEST)
  166. int
  167. testdram(void)
  168. {
  169. uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  170. uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  171. uint *p;
  172. printf("Testing DRAM from 0x%08x to 0x%08x\n",
  173. CONFIG_SYS_MEMTEST_START,
  174. CONFIG_SYS_MEMTEST_END);
  175. printf("DRAM test phase 1:\n");
  176. for (p = pstart; p < pend; p++)
  177. *p = 0xaaaaaaaa;
  178. for (p = pstart; p < pend; p++) {
  179. if (*p != 0xaaaaaaaa) {
  180. printf ("DRAM test fails at: %08x\n", (uint) p);
  181. return 1;
  182. }
  183. }
  184. printf("DRAM test phase 2:\n");
  185. for (p = pstart; p < pend; p++)
  186. *p = 0x55555555;
  187. for (p = pstart; p < pend; p++) {
  188. if (*p != 0x55555555) {
  189. printf ("DRAM test fails at: %08x\n", (uint) p);
  190. return 1;
  191. }
  192. }
  193. printf("DRAM test passed.\n");
  194. return 0;
  195. }
  196. #endif
  197. #ifdef CONFIG_PCI1
  198. static struct pci_controller pci1_hose;
  199. #endif /* CONFIG_PCI1 */
  200. #ifdef CONFIG_PCI
  201. void
  202. pci_init_board(void)
  203. {
  204. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  205. int first_free_busno = 0;
  206. #ifdef CONFIG_PCI1
  207. struct fsl_pci_info pci_info;
  208. u32 devdisr = in_be32(&gur->devdisr);
  209. u32 pordevsr = in_be32(&gur->pordevsr);
  210. u32 porpllsr = in_be32(&gur->porpllsr);
  211. if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
  212. uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
  213. uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
  214. uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
  215. uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
  216. printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
  217. (pci_32) ? 32 : 64,
  218. (pci_speed == 33000000) ? "33" :
  219. (pci_speed == 66000000) ? "66" : "unknown",
  220. pci_clk_sel ? "sync" : "async",
  221. pci_arb ? "arbiter" : "external-arbiter");
  222. SET_STD_PCI_INFO(pci_info, 1);
  223. set_next_law(pci_info.mem_phys,
  224. law_size_bits(pci_info.mem_size), pci_info.law);
  225. set_next_law(pci_info.io_phys,
  226. law_size_bits(pci_info.io_size), pci_info.law);
  227. first_free_busno = fsl_pci_init_port(&pci_info,
  228. &pci1_hose, first_free_busno);
  229. } else {
  230. printf("PCI: disabled\n");
  231. }
  232. puts("\n");
  233. #else
  234. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
  235. #endif
  236. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
  237. fsl_pcie_init_board(first_free_busno);
  238. }
  239. #endif
  240. int board_eth_init(bd_t *bis)
  241. {
  242. tsec_standard_init(bis);
  243. pci_eth_init(bis);
  244. return 0; /* otherwise cpu_eth_init gets run */
  245. }
  246. int last_stage_init(void)
  247. {
  248. return 0;
  249. }
  250. #if defined(CONFIG_OF_BOARD_SETUP)
  251. void ft_board_setup(void *blob, bd_t *bd)
  252. {
  253. ft_cpu_setup(blob, bd);
  254. #ifdef CONFIG_FSL_PCI_INIT
  255. FT_FSL_PCI_SETUP;
  256. #endif
  257. }
  258. #endif