ddr.c 7.3 KB

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  1. /*
  2. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 as published by the Free Software Foundation.
  7. */
  8. #include <common.h>
  9. #include <asm/mmu.h>
  10. #include <asm/immap_85xx.h>
  11. #include <asm/processor.h>
  12. #include <asm/fsl_ddr_sdram.h>
  13. #include <asm/fsl_ddr_dimm_params.h>
  14. #include <asm/io.h>
  15. #include <asm/fsl_law.h>
  16. #ifdef CONFIG_SYS_DDR_RAW_TIMING
  17. #if defined(CONFIG_P1020RDB_PROTO) || \
  18. defined(CONFIG_P1021RDB) || \
  19. defined(CONFIG_P1020UTM)
  20. /* Micron MT41J256M8_187E */
  21. dimm_params_t ddr_raw_timing = {
  22. .n_ranks = 1,
  23. .rank_density = 1073741824u,
  24. .capacity = 1073741824u,
  25. .primary_sdram_width = 32,
  26. .ec_sdram_width = 0,
  27. .registered_dimm = 0,
  28. .mirrored_dimm = 0,
  29. .n_row_addr = 15,
  30. .n_col_addr = 10,
  31. .n_banks_per_sdram_device = 8,
  32. .edc_config = 0,
  33. .burst_lengths_bitmask = 0x0c,
  34. .tCKmin_X_ps = 1870,
  35. .caslat_X = 0x1e << 4, /* 5,6,7,8 */
  36. .tAA_ps = 13125,
  37. .tWR_ps = 15000,
  38. .tRCD_ps = 13125,
  39. .tRRD_ps = 7500,
  40. .tRP_ps = 13125,
  41. .tRAS_ps = 37500,
  42. .tRC_ps = 50625,
  43. .tRFC_ps = 160000,
  44. .tWTR_ps = 7500,
  45. .tRTP_ps = 7500,
  46. .refresh_rate_ps = 7800000,
  47. .tFAW_ps = 37500,
  48. };
  49. #elif defined(CONFIG_P2020RDB)
  50. /* Micron MT41J128M16_15E */
  51. dimm_params_t ddr_raw_timing = {
  52. .n_ranks = 1,
  53. .rank_density = 1073741824u,
  54. .capacity = 1073741824u,
  55. .primary_sdram_width = 64,
  56. .ec_sdram_width = 0,
  57. .registered_dimm = 0,
  58. .mirrored_dimm = 0,
  59. .n_row_addr = 14,
  60. .n_col_addr = 10,
  61. .n_banks_per_sdram_device = 8,
  62. .edc_config = 0,
  63. .burst_lengths_bitmask = 0x0c,
  64. .tCKmin_X_ps = 1500,
  65. .caslat_X = 0x7e << 4, /* 5,6,7,8,9,10 */
  66. .tAA_ps = 13500,
  67. .tWR_ps = 15000,
  68. .tRCD_ps = 13500,
  69. .tRRD_ps = 6000,
  70. .tRP_ps = 13500,
  71. .tRAS_ps = 36000,
  72. .tRC_ps = 49500,
  73. .tRFC_ps = 160000,
  74. .tWTR_ps = 7500,
  75. .tRTP_ps = 7500,
  76. .refresh_rate_ps = 7800000,
  77. .tFAW_ps = 30000,
  78. };
  79. #elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
  80. /* Micron MT41J512M8_187E */
  81. dimm_params_t ddr_raw_timing = {
  82. .n_ranks = 2,
  83. .rank_density = 1073741824u,
  84. .capacity = 2147483648u,
  85. .primary_sdram_width = 32,
  86. .ec_sdram_width = 0,
  87. .registered_dimm = 0,
  88. .mirrored_dimm = 0,
  89. .n_row_addr = 15,
  90. .n_col_addr = 10,
  91. .n_banks_per_sdram_device = 8,
  92. .edc_config = 0,
  93. .burst_lengths_bitmask = 0x0c,
  94. .tCKmin_X_ps = 1870,
  95. .caslat_X = 0x1e << 4, /* 5,6,7,8 */
  96. .tAA_ps = 13125,
  97. .tWR_ps = 15000,
  98. .tRCD_ps = 13125,
  99. .tRRD_ps = 7500,
  100. .tRP_ps = 13125,
  101. .tRAS_ps = 37500,
  102. .tRC_ps = 50625,
  103. .tRFC_ps = 160000,
  104. .tWTR_ps = 7500,
  105. .tRTP_ps = 7500,
  106. .refresh_rate_ps = 7800000,
  107. .tFAW_ps = 37500,
  108. };
  109. #elif defined(CONFIG_P1020RDB_PC)
  110. /*
  111. * Samsung K4B2G0846C-HCF8
  112. * The following timing are for "downshift"
  113. * i.e. to use CL9 part as CL7
  114. * otherwise, tAA, tRCD, tRP will be 13500ps
  115. * and tRC will be 49500ps
  116. */
  117. dimm_params_t ddr_raw_timing = {
  118. .n_ranks = 1,
  119. .rank_density = 1073741824u,
  120. .capacity = 1073741824u,
  121. .primary_sdram_width = 32,
  122. .ec_sdram_width = 0,
  123. .registered_dimm = 0,
  124. .mirrored_dimm = 0,
  125. .n_row_addr = 15,
  126. .n_col_addr = 10,
  127. .n_banks_per_sdram_device = 8,
  128. .edc_config = 0,
  129. .burst_lengths_bitmask = 0x0c,
  130. .tCKmin_X_ps = 1875,
  131. .caslat_X = 0x1e << 4, /* 5,6,7,8 */
  132. .tAA_ps = 13125,
  133. .tWR_ps = 15000,
  134. .tRCD_ps = 13125,
  135. .tRRD_ps = 7500,
  136. .tRP_ps = 13125,
  137. .tRAS_ps = 37500,
  138. .tRC_ps = 50625,
  139. .tRFC_ps = 160000,
  140. .tWTR_ps = 7500,
  141. .tRTP_ps = 7500,
  142. .refresh_rate_ps = 7800000,
  143. .tFAW_ps = 37500,
  144. };
  145. #elif defined(CONFIG_P1024RDB) || \
  146. defined(CONFIG_P1025RDB)
  147. /*
  148. * Samsung K4B2G0846C-HCH9
  149. * The following timing are for "downshift"
  150. * i.e. to use CL9 part as CL7
  151. * otherwise, tAA, tRCD, tRP will be 13500ps
  152. * and tRC will be 49500ps
  153. */
  154. dimm_params_t ddr_raw_timing = {
  155. .n_ranks = 1,
  156. .rank_density = 1073741824u,
  157. .capacity = 1073741824u,
  158. .primary_sdram_width = 32,
  159. .ec_sdram_width = 0,
  160. .registered_dimm = 0,
  161. .mirrored_dimm = 0,
  162. .n_row_addr = 15,
  163. .n_col_addr = 10,
  164. .n_banks_per_sdram_device = 8,
  165. .edc_config = 0,
  166. .burst_lengths_bitmask = 0x0c,
  167. .tCKmin_X_ps = 1500,
  168. .caslat_X = 0x3e << 4, /* 5,6,7,8,9 */
  169. .tAA_ps = 13125,
  170. .tWR_ps = 15000,
  171. .tRCD_ps = 13125,
  172. .tRRD_ps = 6000,
  173. .tRP_ps = 13125,
  174. .tRAS_ps = 36000,
  175. .tRC_ps = 49125,
  176. .tRFC_ps = 160000,
  177. .tWTR_ps = 7500,
  178. .tRTP_ps = 7500,
  179. .refresh_rate_ps = 7800000,
  180. .tFAW_ps = 30000,
  181. };
  182. #else
  183. #error Missing raw timing data for this board
  184. #endif
  185. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  186. unsigned int controller_number,
  187. unsigned int dimm_number)
  188. {
  189. const char dimm_model[] = "Fixed DDR on board";
  190. if ((controller_number == 0) && (dimm_number == 0)) {
  191. memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  192. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  193. memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  194. }
  195. return 0;
  196. }
  197. #endif /* CONFIG_SYS_DDR_RAW_TIMING */
  198. #ifdef CONFIG_SYS_DDR_CS0_BNDS
  199. /* Fixed sdram init -- doesn't use serial presence detect. */
  200. phys_size_t fixed_sdram(void)
  201. {
  202. sys_info_t sysinfo;
  203. char buf[32];
  204. size_t ddr_size;
  205. fsl_ddr_cfg_regs_t ddr_cfg_regs = {
  206. .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  207. .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  208. .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  209. #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
  210. .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
  211. .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
  212. .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
  213. #endif
  214. .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
  215. .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
  216. .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
  217. .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
  218. .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  219. .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  220. .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
  221. .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
  222. .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  223. .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
  224. .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
  225. .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
  226. .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  227. .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  228. .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  229. .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  230. .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  231. .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
  232. .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  233. .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  234. .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  235. };
  236. get_sys_info(&sysinfo);
  237. printf("Configuring DDR for %s MT/s data rate\n",
  238. strmhz(buf, sysinfo.freq_ddrbus));
  239. ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  240. fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
  241. if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  242. ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
  243. printf("ERROR setting Local Access Windows for DDR\n");
  244. return 0;
  245. };
  246. return ddr_size;
  247. }
  248. #endif
  249. void fsl_ddr_board_options(memctl_options_t *popts,
  250. dimm_params_t *pdimm,
  251. unsigned int ctrl_num)
  252. {
  253. int i;
  254. popts->clk_adjust = 6;
  255. popts->cpo_override = 0x1f;
  256. popts->write_data_delay = 2;
  257. popts->half_strength_driver_enable = 1;
  258. /* Write leveling override */
  259. popts->wrlvl_en = 1;
  260. popts->wrlvl_override = 1;
  261. popts->wrlvl_sample = 0xf;
  262. popts->wrlvl_start = 0x8;
  263. popts->trwt_override = 1;
  264. popts->trwt = 0;
  265. if (pdimm->primary_sdram_width == 64)
  266. popts->data_bus_width = 0;
  267. else if (pdimm->primary_sdram_width == 32)
  268. popts->data_bus_width = 1;
  269. else
  270. printf("Error in DDR bus width configuration!\n");
  271. for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  272. popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
  273. popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
  274. }
  275. }