mpc8541cds.c 15 KB

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  1. /*
  2. * Copyright 2004, 2011 Freescale Semiconductor.
  3. *
  4. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <pci.h>
  10. #include <asm/processor.h>
  11. #include <asm/mmu.h>
  12. #include <asm/immap_85xx.h>
  13. #include <asm/fsl_ddr_sdram.h>
  14. #include <ioports.h>
  15. #include <spd_sdram.h>
  16. #include <libfdt.h>
  17. #include <fdt_support.h>
  18. #include "../common/cadmus.h"
  19. #include "../common/eeprom.h"
  20. #include "../common/via.h"
  21. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  22. extern void ddr_enable_ecc(unsigned int dram_size);
  23. #endif
  24. void local_bus_init(void);
  25. /*
  26. * I/O Port configuration table
  27. *
  28. * if conf is 1, then that port pin will be configured at boot time
  29. * according to the five values podr/pdir/ppar/psor/pdat for that entry
  30. */
  31. const iop_conf_t iop_conf_tab[4][32] = {
  32. /* Port A configuration */
  33. { /* conf ppar psor pdir podr pdat */
  34. /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
  35. /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
  36. /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
  37. /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
  38. /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
  39. /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
  40. /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
  41. /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
  42. /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
  43. /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
  44. /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
  45. /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
  46. /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
  47. /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
  48. /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
  49. /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
  50. /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
  51. /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
  52. /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
  53. /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
  54. /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
  55. /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
  56. /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
  57. /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
  58. /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
  59. /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
  60. /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
  61. /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
  62. /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
  63. /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
  64. /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
  65. /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
  66. },
  67. /* Port B configuration */
  68. { /* conf ppar psor pdir podr pdat */
  69. /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
  70. /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
  71. /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
  72. /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
  73. /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
  74. /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
  75. /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
  76. /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
  77. /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
  78. /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
  79. /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
  80. /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
  81. /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
  82. /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
  83. /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
  84. /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
  85. /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
  86. /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
  87. /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
  88. /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
  89. /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  90. /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  91. /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  92. /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  93. /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  94. /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  95. /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  96. /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  97. /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  98. /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  99. /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  100. /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  101. },
  102. /* Port C */
  103. { /* conf ppar psor pdir podr pdat */
  104. /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
  105. /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
  106. /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
  107. /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
  108. /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
  109. /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
  110. /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
  111. /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
  112. /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
  113. /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
  114. /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
  115. /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
  116. /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
  117. /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
  118. /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
  119. /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
  120. /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
  121. /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
  122. /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
  123. /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
  124. /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
  125. /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
  126. /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
  127. /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
  128. /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
  129. /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
  130. /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
  131. /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
  132. /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
  133. /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
  134. /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
  135. /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
  136. },
  137. /* Port D */
  138. { /* conf ppar psor pdir podr pdat */
  139. /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
  140. /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
  141. /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
  142. /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
  143. /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
  144. /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
  145. /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
  146. /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
  147. /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
  148. /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
  149. /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
  150. /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
  151. /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
  152. /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
  153. /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
  154. /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
  155. /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
  156. /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
  157. /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
  158. /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
  159. /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
  160. /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
  161. /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
  162. /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
  163. /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
  164. /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
  165. /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
  166. /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
  167. /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  168. /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  169. /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  170. /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  171. }
  172. };
  173. int checkboard (void)
  174. {
  175. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  176. char buf[32];
  177. /* PCI slot in USER bits CSR[6:7] by convention. */
  178. uint pci_slot = get_pci_slot ();
  179. uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
  180. uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
  181. uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
  182. uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
  183. uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
  184. uint cpu_board_rev = get_cpu_board_revision ();
  185. printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
  186. get_board_version (), pci_slot);
  187. printf ("CPU Board Revision %d.%d (0x%04x)\n",
  188. MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
  189. MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
  190. printf("PCI1: %d bit, %s MHz, %s\n",
  191. (pci1_32) ? 32 : 64,
  192. strmhz(buf, pci1_speed),
  193. pci1_clk_sel ? "sync" : "async");
  194. if (pci_dual) {
  195. printf("PCI2: 32 bit, 66 MHz, %s\n",
  196. pci2_clk_sel ? "sync" : "async");
  197. } else {
  198. printf("PCI2: disabled\n");
  199. }
  200. /*
  201. * Initialize local bus.
  202. */
  203. local_bus_init ();
  204. return 0;
  205. }
  206. /*
  207. * Initialize Local Bus
  208. */
  209. void
  210. local_bus_init(void)
  211. {
  212. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  213. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  214. uint clkdiv;
  215. uint lbc_hz;
  216. sys_info_t sysinfo;
  217. uint temp_lbcdll;
  218. /*
  219. * Errata LBC11.
  220. * Fix Local Bus clock glitch when DLL is enabled.
  221. *
  222. * If localbus freq is < 66MHz, DLL bypass mode must be used.
  223. * If localbus freq is > 133MHz, DLL can be safely enabled.
  224. * Between 66 and 133, the DLL is enabled with an override workaround.
  225. */
  226. get_sys_info(&sysinfo);
  227. clkdiv = lbc->lcrr & LCRR_CLKDIV;
  228. lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
  229. if (lbc_hz < 66) {
  230. lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */
  231. } else if (lbc_hz >= 133) {
  232. lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
  233. } else {
  234. lbc->lcrr &= (~LCRR_DBYP); /* DLL Enabled */
  235. udelay(200);
  236. /*
  237. * Sample LBC DLL ctrl reg, upshift it to set the
  238. * override bits.
  239. */
  240. temp_lbcdll = gur->lbcdllcr;
  241. gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
  242. asm("sync;isync;msync");
  243. }
  244. }
  245. /*
  246. * Initialize SDRAM memory on the Local Bus.
  247. */
  248. void lbc_sdram_init(void)
  249. {
  250. #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
  251. uint idx;
  252. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  253. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  254. uint cpu_board_rev;
  255. uint lsdmr_common;
  256. puts("LBC SDRAM: ");
  257. print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
  258. "\n ");
  259. /*
  260. * Setup SDRAM Base and Option Registers
  261. */
  262. set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  263. set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
  264. lbc->lbcr = CONFIG_SYS_LBC_LBCR;
  265. asm("msync");
  266. lbc->lsrt = CONFIG_SYS_LBC_LSRT;
  267. lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
  268. asm("msync");
  269. /*
  270. * Determine which address lines to use baed on CPU board rev.
  271. */
  272. cpu_board_rev = get_cpu_board_revision();
  273. lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
  274. if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
  275. lsdmr_common |= LSDMR_BSMA1617;
  276. } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
  277. lsdmr_common |= LSDMR_BSMA1516;
  278. } else {
  279. /*
  280. * Assume something unable to identify itself is
  281. * really old, and likely has lines 16/17 mapped.
  282. */
  283. lsdmr_common |= LSDMR_BSMA1617;
  284. }
  285. /*
  286. * Issue PRECHARGE ALL command.
  287. */
  288. lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
  289. asm("sync;msync");
  290. *sdram_addr = 0xff;
  291. ppcDcbf((unsigned long) sdram_addr);
  292. udelay(100);
  293. /*
  294. * Issue 8 AUTO REFRESH commands.
  295. */
  296. for (idx = 0; idx < 8; idx++) {
  297. lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
  298. asm("sync;msync");
  299. *sdram_addr = 0xff;
  300. ppcDcbf((unsigned long) sdram_addr);
  301. udelay(100);
  302. }
  303. /*
  304. * Issue 8 MODE-set command.
  305. */
  306. lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
  307. asm("sync;msync");
  308. *sdram_addr = 0xff;
  309. ppcDcbf((unsigned long) sdram_addr);
  310. udelay(100);
  311. /*
  312. * Issue NORMAL OP command.
  313. */
  314. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  315. asm("sync;msync");
  316. *sdram_addr = 0xff;
  317. ppcDcbf((unsigned long) sdram_addr);
  318. udelay(200); /* Overkill. Must wait > 200 bus cycles */
  319. #endif /* enable SDRAM init */
  320. }
  321. #if defined(CONFIG_PCI)
  322. /* For some reason the Tundra PCI bridge shows up on itself as a
  323. * different device. Work around that by refusing to configure it.
  324. */
  325. void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
  326. static struct pci_config_table pci_mpc85xxcds_config_table[] = {
  327. {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
  328. {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
  329. {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
  330. mpc85xx_config_via_usbide, {0,0,0}},
  331. {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
  332. mpc85xx_config_via_usb, {0,0,0}},
  333. {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
  334. mpc85xx_config_via_usb2, {0,0,0}},
  335. {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
  336. mpc85xx_config_via_power, {0,0,0}},
  337. {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
  338. mpc85xx_config_via_ac97, {0,0,0}},
  339. {},
  340. };
  341. static struct pci_controller hose[] = {
  342. { config_table: pci_mpc85xxcds_config_table,},
  343. #ifdef CONFIG_MPC85XX_PCI2
  344. {},
  345. #endif
  346. };
  347. #endif /* CONFIG_PCI */
  348. void
  349. pci_init_board(void)
  350. {
  351. #ifdef CONFIG_PCI
  352. pci_mpc85xx_init(hose);
  353. #endif
  354. }
  355. #if defined(CONFIG_OF_BOARD_SETUP)
  356. void
  357. ft_pci_setup(void *blob, bd_t *bd)
  358. {
  359. int node, tmp[2];
  360. const char *path;
  361. node = fdt_path_offset(blob, "/aliases");
  362. tmp[0] = 0;
  363. if (node >= 0) {
  364. #ifdef CONFIG_PCI1
  365. path = fdt_getprop(blob, node, "pci0", NULL);
  366. if (path) {
  367. tmp[1] = hose[0].last_busno - hose[0].first_busno;
  368. do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
  369. }
  370. #endif
  371. #ifdef CONFIG_MPC85XX_PCI2
  372. path = fdt_getprop(blob, node, "pci1", NULL);
  373. if (path) {
  374. tmp[1] = hose[1].last_busno - hose[1].first_busno;
  375. do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
  376. }
  377. #endif
  378. }
  379. }
  380. #endif