mpc8540ads.c 5.1 KB

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  1. /*
  2. * Copyright 2004 Freescale Semiconductor.
  3. * (C) Copyright 2002,2003, Motorola Inc.
  4. * Xianghua Xiao, (X.Xiao@motorola.com)
  5. *
  6. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <common.h>
  11. #include <pci.h>
  12. #include <asm/processor.h>
  13. #include <asm/mmu.h>
  14. #include <asm/immap_85xx.h>
  15. #include <asm/fsl_ddr_sdram.h>
  16. #include <libfdt.h>
  17. #include <fdt_support.h>
  18. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  19. extern void ddr_enable_ecc(unsigned int dram_size);
  20. #endif
  21. void local_bus_init(void);
  22. int checkboard (void)
  23. {
  24. puts("Board: ADS\n");
  25. #ifdef CONFIG_PCI
  26. printf("PCI1: 32 bit, %d MHz (compiled)\n",
  27. CONFIG_SYS_CLK_FREQ / 1000000);
  28. #else
  29. printf("PCI1: disabled\n");
  30. #endif
  31. /*
  32. * Initialize local bus.
  33. */
  34. local_bus_init();
  35. return 0;
  36. }
  37. /*
  38. * Initialize Local Bus
  39. */
  40. void
  41. local_bus_init(void)
  42. {
  43. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  44. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  45. uint clkdiv;
  46. uint lbc_hz;
  47. sys_info_t sysinfo;
  48. /*
  49. * Errata LBC11.
  50. * Fix Local Bus clock glitch when DLL is enabled.
  51. *
  52. * If localbus freq is < 66MHz, DLL bypass mode must be used.
  53. * If localbus freq is > 133MHz, DLL can be safely enabled.
  54. * Between 66 and 133, the DLL is enabled with an override workaround.
  55. */
  56. get_sys_info(&sysinfo);
  57. clkdiv = lbc->lcrr & LCRR_CLKDIV;
  58. lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
  59. if (lbc_hz < 66) {
  60. lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
  61. } else if (lbc_hz >= 133) {
  62. lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
  63. } else {
  64. /*
  65. * On REV1 boards, need to change CLKDIV before enable DLL.
  66. * Default CLKDIV is 8, change it to 4 temporarily.
  67. */
  68. uint pvr = get_pvr();
  69. uint temp_lbcdll = 0;
  70. if (pvr == PVR_85xx_REV1) {
  71. /* FIXME: Justify the high bit here. */
  72. lbc->lcrr = 0x10000004;
  73. }
  74. lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
  75. udelay(200);
  76. /*
  77. * Sample LBC DLL ctrl reg, upshift it to set the
  78. * override bits.
  79. */
  80. temp_lbcdll = gur->lbcdllcr;
  81. gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
  82. asm("sync;isync;msync");
  83. }
  84. }
  85. /*
  86. * Initialize SDRAM memory on the Local Bus.
  87. */
  88. void lbc_sdram_init(void)
  89. {
  90. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  91. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  92. puts("LBC SDRAM: ");
  93. print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
  94. "\n ");
  95. /*
  96. * Setup SDRAM Base and Option Registers
  97. */
  98. set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  99. set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
  100. lbc->lbcr = CONFIG_SYS_LBC_LBCR;
  101. asm("msync");
  102. lbc->lsrt = CONFIG_SYS_LBC_LSRT;
  103. lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
  104. asm("sync");
  105. /*
  106. * Configure the SDRAM controller.
  107. */
  108. lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
  109. asm("sync");
  110. *sdram_addr = 0xff;
  111. ppcDcbf((unsigned long) sdram_addr);
  112. udelay(100);
  113. lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
  114. asm("sync");
  115. *sdram_addr = 0xff;
  116. ppcDcbf((unsigned long) sdram_addr);
  117. udelay(100);
  118. lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
  119. asm("sync");
  120. *sdram_addr = 0xff;
  121. ppcDcbf((unsigned long) sdram_addr);
  122. udelay(100);
  123. lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
  124. asm("sync");
  125. *sdram_addr = 0xff;
  126. ppcDcbf((unsigned long) sdram_addr);
  127. udelay(100);
  128. lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
  129. asm("sync");
  130. *sdram_addr = 0xff;
  131. ppcDcbf((unsigned long) sdram_addr);
  132. udelay(100);
  133. }
  134. #if !defined(CONFIG_SPD_EEPROM)
  135. /*************************************************************************
  136. * fixed sdram init -- doesn't use serial presence detect.
  137. ************************************************************************/
  138. phys_size_t fixed_sdram(void)
  139. {
  140. #ifndef CONFIG_SYS_RAMBOOT
  141. volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
  142. ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  143. ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  144. ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  145. ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  146. ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
  147. ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  148. #if defined (CONFIG_DDR_ECC)
  149. ddr->err_disable = 0x0000000D;
  150. ddr->err_sbe = 0x00ff0000;
  151. #endif
  152. asm("sync;isync;msync");
  153. udelay(500);
  154. #if defined (CONFIG_DDR_ECC)
  155. /* Enable ECC checking */
  156. ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
  157. #else
  158. ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
  159. #endif
  160. asm("sync; isync; msync");
  161. udelay(500);
  162. #endif
  163. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  164. }
  165. #endif /* !defined(CONFIG_SPD_EEPROM) */
  166. #if defined(CONFIG_PCI)
  167. /*
  168. * Initialize PCI Devices, report devices found.
  169. */
  170. static struct pci_controller hose;
  171. #endif /* CONFIG_PCI */
  172. void
  173. pci_init_board(void)
  174. {
  175. #ifdef CONFIG_PCI
  176. pci_mpc85xx_init(&hose);
  177. #endif /* CONFIG_PCI */
  178. }
  179. #if defined(CONFIG_OF_BOARD_SETUP)
  180. void
  181. ft_board_setup(void *blob, bd_t *bd)
  182. {
  183. int node, tmp[2];
  184. const char *path;
  185. ft_cpu_setup(blob, bd);
  186. node = fdt_path_offset(blob, "/aliases");
  187. tmp[0] = 0;
  188. if (node >= 0) {
  189. #ifdef CONFIG_PCI
  190. path = fdt_getprop(blob, node, "pci0", NULL);
  191. if (path) {
  192. tmp[1] = hose.last_busno - hose.first_busno;
  193. do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
  194. }
  195. #endif
  196. }
  197. }
  198. #endif