speed.c 13 KB

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  1. /*
  2. * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
  3. *
  4. * (C) Copyright 2003 Motorola Inc.
  5. * Xianghua Xiao, (X.Xiao@motorola.com)
  6. *
  7. * (C) Copyright 2000
  8. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. #include <common.h>
  13. #include <ppc_asm.tmpl>
  14. #include <linux/compiler.h>
  15. #include <asm/processor.h>
  16. #include <asm/io.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. /* --------------------------------------------------------------- */
  19. void get_sys_info(sys_info_t *sys_info)
  20. {
  21. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  22. #ifdef CONFIG_FSL_IFC
  23. struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
  24. u32 ccr;
  25. #endif
  26. #ifdef CONFIG_FSL_CORENET
  27. volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
  28. unsigned int cpu;
  29. const u8 core_cplx_PLL[16] = {
  30. [ 0] = 0, /* CC1 PPL / 1 */
  31. [ 1] = 0, /* CC1 PPL / 2 */
  32. [ 2] = 0, /* CC1 PPL / 4 */
  33. [ 4] = 1, /* CC2 PPL / 1 */
  34. [ 5] = 1, /* CC2 PPL / 2 */
  35. [ 6] = 1, /* CC2 PPL / 4 */
  36. [ 8] = 2, /* CC3 PPL / 1 */
  37. [ 9] = 2, /* CC3 PPL / 2 */
  38. [10] = 2, /* CC3 PPL / 4 */
  39. [12] = 3, /* CC4 PPL / 1 */
  40. [13] = 3, /* CC4 PPL / 2 */
  41. [14] = 3, /* CC4 PPL / 4 */
  42. };
  43. const u8 core_cplx_pll_div[16] = {
  44. [ 0] = 1, /* CC1 PPL / 1 */
  45. [ 1] = 2, /* CC1 PPL / 2 */
  46. [ 2] = 4, /* CC1 PPL / 4 */
  47. [ 4] = 1, /* CC2 PPL / 1 */
  48. [ 5] = 2, /* CC2 PPL / 2 */
  49. [ 6] = 4, /* CC2 PPL / 4 */
  50. [ 8] = 1, /* CC3 PPL / 1 */
  51. [ 9] = 2, /* CC3 PPL / 2 */
  52. [10] = 4, /* CC3 PPL / 4 */
  53. [12] = 1, /* CC4 PPL / 1 */
  54. [13] = 2, /* CC4 PPL / 2 */
  55. [14] = 4, /* CC4 PPL / 4 */
  56. };
  57. uint i, freq_cc_pll[6], rcw_tmp;
  58. uint ratio[6];
  59. unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
  60. uint mem_pll_rat;
  61. sys_info->freq_systembus = sysclk;
  62. #ifdef CONFIG_DDR_CLK_FREQ
  63. sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
  64. #else
  65. sys_info->freq_ddrbus = sysclk;
  66. #endif
  67. sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  68. mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
  69. FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
  70. & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  71. if (mem_pll_rat > 2)
  72. sys_info->freq_ddrbus *= mem_pll_rat;
  73. else
  74. sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
  75. ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
  76. ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
  77. ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
  78. ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
  79. ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
  80. ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
  81. for (i = 0; i < 6; i++) {
  82. if (ratio[i] > 4)
  83. freq_cc_pll[i] = sysclk * ratio[i];
  84. else
  85. freq_cc_pll[i] = sys_info->freq_systembus * ratio[i];
  86. }
  87. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  88. /*
  89. * Each cluster has up to 4 cores, sharing the same PLL selection.
  90. * The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are
  91. * cluster group A, feeding cores on cluster 1 and cluster 2.
  92. * PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3
  93. * and cluster 4 if existing.
  94. */
  95. for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
  96. int cluster = fsl_qoriq_core_to_cluster(cpu);
  97. u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
  98. & 0xf;
  99. u32 cplx_pll = core_cplx_PLL[c_pll_sel];
  100. if (cplx_pll > 3)
  101. printf("Unsupported architecture configuration"
  102. " in function %s\n", __func__);
  103. cplx_pll += (cluster / 2) * 3;
  104. sys_info->freq_processor[cpu] =
  105. freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  106. }
  107. #ifdef CONFIG_PPC_B4860
  108. #define FM1_CLK_SEL 0xe0000000
  109. #define FM1_CLK_SHIFT 29
  110. #else
  111. #define PME_CLK_SEL 0xe0000000
  112. #define PME_CLK_SHIFT 29
  113. #define FM1_CLK_SEL 0x1c000000
  114. #define FM1_CLK_SHIFT 26
  115. #endif
  116. rcw_tmp = in_be32(&gur->rcwsr[7]);
  117. #ifdef CONFIG_SYS_DPAA_PME
  118. switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
  119. case 1:
  120. sys_info->freq_pme = freq_cc_pll[0];
  121. break;
  122. case 2:
  123. sys_info->freq_pme = freq_cc_pll[0] / 2;
  124. break;
  125. case 3:
  126. sys_info->freq_pme = freq_cc_pll[0] / 3;
  127. break;
  128. case 4:
  129. sys_info->freq_pme = freq_cc_pll[0] / 4;
  130. break;
  131. case 6:
  132. sys_info->freq_pme = freq_cc_pll[1] / 2;
  133. break;
  134. case 7:
  135. sys_info->freq_pme = freq_cc_pll[1] / 3;
  136. break;
  137. default:
  138. printf("Error: Unknown PME clock select!\n");
  139. case 0:
  140. sys_info->freq_pme = sys_info->freq_systembus / 2;
  141. break;
  142. }
  143. #endif
  144. #ifdef CONFIG_SYS_DPAA_QBMAN
  145. sys_info->freq_qman = sys_info->freq_systembus / 2;
  146. #endif
  147. #ifdef CONFIG_SYS_DPAA_FMAN
  148. switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
  149. case 1:
  150. sys_info->freq_fman[0] = freq_cc_pll[3];
  151. break;
  152. case 2:
  153. sys_info->freq_fman[0] = freq_cc_pll[3] / 2;
  154. break;
  155. case 3:
  156. sys_info->freq_fman[0] = freq_cc_pll[3] / 3;
  157. break;
  158. case 4:
  159. sys_info->freq_fman[0] = freq_cc_pll[3] / 4;
  160. break;
  161. case 5:
  162. sys_info->freq_fman[0] = sys_info->freq_systembus;
  163. break;
  164. case 6:
  165. sys_info->freq_fman[0] = freq_cc_pll[4] / 2;
  166. break;
  167. case 7:
  168. sys_info->freq_fman[0] = freq_cc_pll[4] / 3;
  169. break;
  170. default:
  171. printf("Error: Unknown FMan1 clock select!\n");
  172. case 0:
  173. sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
  174. break;
  175. }
  176. #if (CONFIG_SYS_NUM_FMAN) == 2
  177. #define FM2_CLK_SEL 0x00000038
  178. #define FM2_CLK_SHIFT 3
  179. rcw_tmp = in_be32(&gur->rcwsr[15]);
  180. switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
  181. case 1:
  182. sys_info->freq_fman[1] = freq_cc_pll[4];
  183. break;
  184. case 2:
  185. sys_info->freq_fman[1] = freq_cc_pll[4] / 2;
  186. break;
  187. case 3:
  188. sys_info->freq_fman[1] = freq_cc_pll[4] / 3;
  189. break;
  190. case 4:
  191. sys_info->freq_fman[1] = freq_cc_pll[4] / 4;
  192. break;
  193. case 6:
  194. sys_info->freq_fman[1] = freq_cc_pll[3] / 2;
  195. break;
  196. case 7:
  197. sys_info->freq_fman[1] = freq_cc_pll[3] / 3;
  198. break;
  199. default:
  200. printf("Error: Unknown FMan2 clock select!\n");
  201. case 0:
  202. sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
  203. break;
  204. }
  205. #endif /* CONFIG_SYS_NUM_FMAN == 2 */
  206. #endif /* CONFIG_SYS_DPAA_FMAN */
  207. #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  208. for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
  209. u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
  210. & 0xf;
  211. u32 cplx_pll = core_cplx_PLL[c_pll_sel];
  212. sys_info->freq_processor[cpu] =
  213. freq_cc_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
  214. }
  215. #define PME_CLK_SEL 0x80000000
  216. #define FM1_CLK_SEL 0x40000000
  217. #define FM2_CLK_SEL 0x20000000
  218. #define HWA_ASYNC_DIV 0x04000000
  219. #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
  220. #define HWA_CC_PLL 1
  221. #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
  222. #define HWA_CC_PLL 2
  223. #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
  224. #define HWA_CC_PLL 2
  225. #else
  226. #error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
  227. #endif
  228. rcw_tmp = in_be32(&gur->rcwsr[7]);
  229. #ifdef CONFIG_SYS_DPAA_PME
  230. if (rcw_tmp & PME_CLK_SEL) {
  231. if (rcw_tmp & HWA_ASYNC_DIV)
  232. sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 4;
  233. else
  234. sys_info->freq_pme = freq_cc_pll[HWA_CC_PLL] / 2;
  235. } else {
  236. sys_info->freq_pme = sys_info->freq_systembus / 2;
  237. }
  238. #endif
  239. #ifdef CONFIG_SYS_DPAA_FMAN
  240. if (rcw_tmp & FM1_CLK_SEL) {
  241. if (rcw_tmp & HWA_ASYNC_DIV)
  242. sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 4;
  243. else
  244. sys_info->freq_fman[0] = freq_cc_pll[HWA_CC_PLL] / 2;
  245. } else {
  246. sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
  247. }
  248. #if (CONFIG_SYS_NUM_FMAN) == 2
  249. if (rcw_tmp & FM2_CLK_SEL) {
  250. if (rcw_tmp & HWA_ASYNC_DIV)
  251. sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 4;
  252. else
  253. sys_info->freq_fman[1] = freq_cc_pll[HWA_CC_PLL] / 2;
  254. } else {
  255. sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
  256. }
  257. #endif
  258. #endif
  259. #ifdef CONFIG_SYS_DPAA_QBMAN
  260. sys_info->freq_qman = sys_info->freq_systembus / 2;
  261. #endif
  262. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  263. #else /* CONFIG_FSL_CORENET */
  264. uint plat_ratio, e500_ratio, half_freq_systembus;
  265. int i;
  266. #ifdef CONFIG_QE
  267. __maybe_unused u32 qe_ratio;
  268. #endif
  269. plat_ratio = (gur->porpllsr) & 0x0000003e;
  270. plat_ratio >>= 1;
  271. sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
  272. /* Divide before multiply to avoid integer
  273. * overflow for processor speeds above 2GHz */
  274. half_freq_systembus = sys_info->freq_systembus/2;
  275. for (i = 0; i < cpu_numcores(); i++) {
  276. e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
  277. sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
  278. }
  279. /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
  280. sys_info->freq_ddrbus = sys_info->freq_systembus;
  281. #ifdef CONFIG_DDR_CLK_FREQ
  282. {
  283. u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  284. >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  285. if (ddr_ratio != 0x7)
  286. sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
  287. }
  288. #endif
  289. #ifdef CONFIG_QE
  290. #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
  291. sys_info->freq_qe = sys_info->freq_systembus;
  292. #else
  293. qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
  294. >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
  295. sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
  296. #endif
  297. #endif
  298. #ifdef CONFIG_SYS_DPAA_FMAN
  299. sys_info->freq_fman[0] = sys_info->freq_systembus;
  300. #endif
  301. #endif /* CONFIG_FSL_CORENET */
  302. #if defined(CONFIG_FSL_LBC)
  303. uint lcrr_div;
  304. #if defined(CONFIG_SYS_LBC_LCRR)
  305. /* We will program LCRR to this value later */
  306. lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
  307. #else
  308. lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
  309. #endif
  310. if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
  311. #if defined(CONFIG_FSL_CORENET)
  312. /* If this is corenet based SoC, bit-representation
  313. * for four times the clock divider values.
  314. */
  315. lcrr_div *= 4;
  316. #elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
  317. !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
  318. /*
  319. * Yes, the entire PQ38 family use the same
  320. * bit-representation for twice the clock divider values.
  321. */
  322. lcrr_div *= 2;
  323. #endif
  324. sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
  325. } else {
  326. /* In case anyone cares what the unknown value is */
  327. sys_info->freq_localbus = lcrr_div;
  328. }
  329. #endif
  330. #if defined(CONFIG_FSL_IFC)
  331. ccr = in_be32(&ifc_regs->ifc_ccr);
  332. ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
  333. sys_info->freq_localbus = sys_info->freq_systembus / ccr;
  334. #endif
  335. }
  336. int get_clocks (void)
  337. {
  338. sys_info_t sys_info;
  339. #ifdef CONFIG_MPC8544
  340. volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
  341. #endif
  342. #if defined(CONFIG_CPM2)
  343. volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
  344. uint sccr, dfbrg;
  345. /* set VCO = 4 * BRG */
  346. cpm->im_cpm_intctl.sccr &= 0xfffffffc;
  347. sccr = cpm->im_cpm_intctl.sccr;
  348. dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
  349. #endif
  350. get_sys_info (&sys_info);
  351. gd->cpu_clk = sys_info.freq_processor[0];
  352. gd->bus_clk = sys_info.freq_systembus;
  353. gd->mem_clk = sys_info.freq_ddrbus;
  354. gd->arch.lbc_clk = sys_info.freq_localbus;
  355. #ifdef CONFIG_QE
  356. gd->arch.qe_clk = sys_info.freq_qe;
  357. gd->arch.brg_clk = gd->arch.qe_clk / 2;
  358. #endif
  359. /*
  360. * The base clock for I2C depends on the actual SOC. Unfortunately,
  361. * there is no pattern that can be used to determine the frequency, so
  362. * the only choice is to look up the actual SOC number and use the value
  363. * for that SOC. This information is taken from application note
  364. * AN2919.
  365. */
  366. #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
  367. defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
  368. gd->arch.i2c1_clk = sys_info.freq_systembus;
  369. #elif defined(CONFIG_MPC8544)
  370. /*
  371. * On the 8544, the I2C clock is the same as the SEC clock. This can be
  372. * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
  373. * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
  374. * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
  375. * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
  376. */
  377. if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
  378. gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
  379. else
  380. gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
  381. #else
  382. /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
  383. gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
  384. #endif
  385. gd->arch.i2c2_clk = gd->arch.i2c1_clk;
  386. #if defined(CONFIG_FSL_ESDHC)
  387. #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
  388. defined(CONFIG_P1014)
  389. gd->arch.sdhc_clk = gd->bus_clk;
  390. #else
  391. gd->arch.sdhc_clk = gd->bus_clk / 2;
  392. #endif
  393. #endif /* defined(CONFIG_FSL_ESDHC) */
  394. #if defined(CONFIG_CPM2)
  395. gd->arch.vco_out = 2*sys_info.freq_systembus;
  396. gd->arch.cpm_clk = gd->arch.vco_out / 2;
  397. gd->arch.scc_clk = gd->arch.vco_out / 4;
  398. gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
  399. #endif
  400. if(gd->cpu_clk != 0) return (0);
  401. else return (1);
  402. }
  403. /********************************************
  404. * get_bus_freq
  405. * return system bus freq in Hz
  406. *********************************************/
  407. ulong get_bus_freq (ulong dummy)
  408. {
  409. return gd->bus_clk;
  410. }
  411. /********************************************
  412. * get_ddr_freq
  413. * return ddr bus freq in Hz
  414. *********************************************/
  415. ulong get_ddr_freq (ulong dummy)
  416. {
  417. return gd->mem_clk;
  418. }