cpu.c 14 KB

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  1. /*
  2. * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
  3. * (C) Copyright 2002, 2003 Motorola Inc.
  4. * Xianghua Xiao (X.Xiao@motorola.com)
  5. *
  6. * (C) Copyright 2000
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #include <config.h>
  12. #include <common.h>
  13. #include <watchdog.h>
  14. #include <command.h>
  15. #include <fsl_esdhc.h>
  16. #include <asm/cache.h>
  17. #include <asm/io.h>
  18. #include <asm/mmu.h>
  19. #include <asm/fsl_ifc.h>
  20. #include <asm/fsl_law.h>
  21. #include <asm/fsl_lbc.h>
  22. #include <post.h>
  23. #include <asm/processor.h>
  24. #include <asm/fsl_ddr_sdram.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. /*
  27. * Default board reset function
  28. */
  29. static void
  30. __board_reset(void)
  31. {
  32. /* Do nothing */
  33. }
  34. void board_reset(void) __attribute__((weak, alias("__board_reset")));
  35. int checkcpu (void)
  36. {
  37. sys_info_t sysinfo;
  38. uint pvr, svr;
  39. uint ver;
  40. uint major, minor;
  41. struct cpu_type *cpu;
  42. char buf1[32], buf2[32];
  43. #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
  44. ccsr_gur_t __iomem *gur =
  45. (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  46. #endif
  47. /*
  48. * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
  49. * mode. Previous platform use ddr ratio to do the same. This
  50. * information is only for display here.
  51. */
  52. #ifdef CONFIG_FSL_CORENET
  53. #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  54. u32 ddr_sync = 0; /* only async mode is supported */
  55. #else
  56. u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
  57. >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
  58. #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
  59. #else /* CONFIG_FSL_CORENET */
  60. #ifdef CONFIG_DDR_CLK_FREQ
  61. u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  62. >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  63. #else
  64. u32 ddr_ratio = 0;
  65. #endif /* CONFIG_DDR_CLK_FREQ */
  66. #endif /* CONFIG_FSL_CORENET */
  67. unsigned int i, core, nr_cores = cpu_numcores();
  68. u32 mask = cpu_mask();
  69. svr = get_svr();
  70. major = SVR_MAJ(svr);
  71. minor = SVR_MIN(svr);
  72. if (cpu_numcores() > 1) {
  73. #ifndef CONFIG_MP
  74. puts("Unicore software on multiprocessor system!!\n"
  75. "To enable mutlticore build define CONFIG_MP\n");
  76. #endif
  77. volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  78. printf("CPU%d: ", pic->whoami);
  79. } else {
  80. puts("CPU: ");
  81. }
  82. cpu = gd->arch.cpu;
  83. puts(cpu->name);
  84. if (IS_E_PROCESSOR(svr))
  85. puts("E");
  86. printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  87. pvr = get_pvr();
  88. ver = PVR_VER(pvr);
  89. major = PVR_MAJ(pvr);
  90. minor = PVR_MIN(pvr);
  91. printf("Core: ");
  92. switch(ver) {
  93. case PVR_VER_E500_V1:
  94. case PVR_VER_E500_V2:
  95. puts("e500");
  96. break;
  97. case PVR_VER_E500MC:
  98. puts("e500mc");
  99. break;
  100. case PVR_VER_E5500:
  101. puts("e5500");
  102. break;
  103. case PVR_VER_E6500:
  104. puts("e6500");
  105. break;
  106. default:
  107. puts("Unknown");
  108. break;
  109. }
  110. printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
  111. if (nr_cores > CONFIG_MAX_CPUS) {
  112. panic("\nUnexpected number of cores: %d, max is %d\n",
  113. nr_cores, CONFIG_MAX_CPUS);
  114. }
  115. get_sys_info(&sysinfo);
  116. puts("Clock Configuration:");
  117. for_each_cpu(i, core, nr_cores, mask) {
  118. if (!(i & 3))
  119. printf ("\n ");
  120. printf("CPU%d:%-4s MHz, ", core,
  121. strmhz(buf1, sysinfo.freq_processor[core]));
  122. }
  123. printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
  124. printf("\n");
  125. #ifdef CONFIG_FSL_CORENET
  126. if (ddr_sync == 1) {
  127. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  128. "(Synchronous), ",
  129. strmhz(buf1, sysinfo.freq_ddrbus/2),
  130. strmhz(buf2, sysinfo.freq_ddrbus));
  131. } else {
  132. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  133. "(Asynchronous), ",
  134. strmhz(buf1, sysinfo.freq_ddrbus/2),
  135. strmhz(buf2, sysinfo.freq_ddrbus));
  136. }
  137. #else
  138. switch (ddr_ratio) {
  139. case 0x0:
  140. printf(" DDR:%-4s MHz (%s MT/s data rate), ",
  141. strmhz(buf1, sysinfo.freq_ddrbus/2),
  142. strmhz(buf2, sysinfo.freq_ddrbus));
  143. break;
  144. case 0x7:
  145. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  146. "(Synchronous), ",
  147. strmhz(buf1, sysinfo.freq_ddrbus/2),
  148. strmhz(buf2, sysinfo.freq_ddrbus));
  149. break;
  150. default:
  151. printf(" DDR:%-4s MHz (%s MT/s data rate) "
  152. "(Asynchronous), ",
  153. strmhz(buf1, sysinfo.freq_ddrbus/2),
  154. strmhz(buf2, sysinfo.freq_ddrbus));
  155. break;
  156. }
  157. #endif
  158. #if defined(CONFIG_FSL_LBC)
  159. if (sysinfo.freq_localbus > LCRR_CLKDIV) {
  160. printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  161. } else {
  162. printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
  163. sysinfo.freq_localbus);
  164. }
  165. #endif
  166. #if defined(CONFIG_FSL_IFC)
  167. printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
  168. #endif
  169. #ifdef CONFIG_CPM2
  170. printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
  171. #endif
  172. #ifdef CONFIG_QE
  173. printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
  174. #endif
  175. #ifdef CONFIG_SYS_DPAA_FMAN
  176. for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
  177. printf(" FMAN%d: %s MHz\n", i + 1,
  178. strmhz(buf1, sysinfo.freq_fman[i]));
  179. }
  180. #endif
  181. #ifdef CONFIG_SYS_DPAA_QBMAN
  182. printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
  183. #endif
  184. #ifdef CONFIG_SYS_DPAA_PME
  185. printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
  186. #endif
  187. puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
  188. #ifdef CONFIG_FSL_CORENET
  189. /* Display the RCW, so that no one gets confused as to what RCW
  190. * we're actually using for this boot.
  191. */
  192. puts("Reset Configuration Word (RCW):");
  193. for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
  194. u32 rcw = in_be32(&gur->rcwsr[i]);
  195. if ((i % 4) == 0)
  196. printf("\n %08x:", i * 4);
  197. printf(" %08x", rcw);
  198. }
  199. puts("\n");
  200. #endif
  201. return 0;
  202. }
  203. /* ------------------------------------------------------------------------- */
  204. int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  205. {
  206. /* Everything after the first generation of PQ3 parts has RSTCR */
  207. #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
  208. defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
  209. unsigned long val, msr;
  210. /*
  211. * Initiate hard reset in debug control register DBCR0
  212. * Make sure MSR[DE] = 1. This only resets the core.
  213. */
  214. msr = mfmsr ();
  215. msr |= MSR_DE;
  216. mtmsr (msr);
  217. val = mfspr(DBCR0);
  218. val |= 0x70000000;
  219. mtspr(DBCR0,val);
  220. #else
  221. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  222. /* Attempt board-specific reset */
  223. board_reset();
  224. /* Next try asserting HRESET_REQ */
  225. out_be32(&gur->rstcr, 0x2);
  226. udelay(100);
  227. #endif
  228. return 1;
  229. }
  230. /*
  231. * Get timebase clock frequency
  232. */
  233. #ifndef CONFIG_SYS_FSL_TBCLK_DIV
  234. #define CONFIG_SYS_FSL_TBCLK_DIV 8
  235. #endif
  236. unsigned long get_tbclk (void)
  237. {
  238. unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
  239. return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
  240. }
  241. #if defined(CONFIG_WATCHDOG)
  242. void
  243. reset_85xx_watchdog(void)
  244. {
  245. /*
  246. * Clear TSR(WIS) bit by writing 1
  247. */
  248. mtspr(SPRN_TSR, TSR_WIS);
  249. }
  250. void
  251. watchdog_reset(void)
  252. {
  253. int re_enable = disable_interrupts();
  254. reset_85xx_watchdog();
  255. if (re_enable)
  256. enable_interrupts();
  257. }
  258. #endif /* CONFIG_WATCHDOG */
  259. /*
  260. * Initializes on-chip MMC controllers.
  261. * to override, implement board_mmc_init()
  262. */
  263. int cpu_mmc_init(bd_t *bis)
  264. {
  265. #ifdef CONFIG_FSL_ESDHC
  266. return fsl_esdhc_mmc_init(bis);
  267. #else
  268. return 0;
  269. #endif
  270. }
  271. /*
  272. * Print out the state of various machine registers.
  273. * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
  274. * parameters for IFC and TLBs
  275. */
  276. void mpc85xx_reginfo(void)
  277. {
  278. print_tlbcam();
  279. print_laws();
  280. #if defined(CONFIG_FSL_LBC)
  281. print_lbc_regs();
  282. #endif
  283. #ifdef CONFIG_FSL_IFC
  284. print_ifc_regs();
  285. #endif
  286. }
  287. /* Common ddr init for non-corenet fsl 85xx platforms */
  288. #ifndef CONFIG_FSL_CORENET
  289. #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
  290. !defined(CONFIG_SYS_INIT_L2_ADDR)
  291. phys_size_t initdram(int board_type)
  292. {
  293. #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
  294. return fsl_ddr_sdram_size();
  295. #else
  296. return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  297. #endif
  298. }
  299. #else /* CONFIG_SYS_RAMBOOT */
  300. phys_size_t initdram(int board_type)
  301. {
  302. phys_size_t dram_size = 0;
  303. #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
  304. {
  305. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  306. unsigned int x = 10;
  307. unsigned int i;
  308. /*
  309. * Work around to stabilize DDR DLL
  310. */
  311. out_be32(&gur->ddrdllcr, 0x81000000);
  312. asm("sync;isync;msync");
  313. udelay(200);
  314. while (in_be32(&gur->ddrdllcr) != 0x81000100) {
  315. setbits_be32(&gur->devdisr, 0x00010000);
  316. for (i = 0; i < x; i++)
  317. ;
  318. clrbits_be32(&gur->devdisr, 0x00010000);
  319. x++;
  320. }
  321. }
  322. #endif
  323. #if defined(CONFIG_SPD_EEPROM) || \
  324. defined(CONFIG_DDR_SPD) || \
  325. defined(CONFIG_SYS_DDR_RAW_TIMING)
  326. dram_size = fsl_ddr_sdram();
  327. #else
  328. dram_size = fixed_sdram();
  329. #endif
  330. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  331. dram_size *= 0x100000;
  332. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  333. /*
  334. * Initialize and enable DDR ECC.
  335. */
  336. ddr_enable_ecc(dram_size);
  337. #endif
  338. #if defined(CONFIG_FSL_LBC)
  339. /* Some boards also have sdram on the lbc */
  340. lbc_sdram_init();
  341. #endif
  342. debug("DDR: ");
  343. return dram_size;
  344. }
  345. #endif /* CONFIG_SYS_RAMBOOT */
  346. #endif
  347. #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
  348. /* Board-specific functions defined in each board's ddr.c */
  349. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  350. unsigned int ctrl_num);
  351. void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
  352. phys_addr_t *rpn);
  353. unsigned int
  354. setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
  355. void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
  356. static void dump_spd_ddr_reg(void)
  357. {
  358. int i, j, k, m;
  359. u8 *p_8;
  360. u32 *p_32;
  361. ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
  362. generic_spd_eeprom_t
  363. spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
  364. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
  365. fsl_ddr_get_spd(spd[i], i);
  366. puts("SPD data of all dimms (zero vaule is omitted)...\n");
  367. puts("Byte (hex) ");
  368. k = 1;
  369. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  370. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
  371. printf("Dimm%d ", k++);
  372. }
  373. puts("\n");
  374. for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
  375. m = 0;
  376. printf("%3d (0x%02x) ", k, k);
  377. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  378. for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
  379. p_8 = (u8 *) &spd[i][j];
  380. if (p_8[k]) {
  381. printf("0x%02x ", p_8[k]);
  382. m++;
  383. } else
  384. puts(" ");
  385. }
  386. }
  387. if (m)
  388. puts("\n");
  389. else
  390. puts("\r");
  391. }
  392. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  393. switch (i) {
  394. case 0:
  395. ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
  396. break;
  397. #if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  398. case 1:
  399. ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
  400. break;
  401. #endif
  402. #if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  403. case 2:
  404. ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
  405. break;
  406. #endif
  407. #if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  408. case 3:
  409. ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
  410. break;
  411. #endif
  412. default:
  413. printf("%s unexpected controller number = %u\n",
  414. __func__, i);
  415. return;
  416. }
  417. }
  418. printf("DDR registers dump for all controllers "
  419. "(zero vaule is omitted)...\n");
  420. puts("Offset (hex) ");
  421. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
  422. printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
  423. puts("\n");
  424. for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
  425. m = 0;
  426. printf("%6d (0x%04x)", k * 4, k * 4);
  427. for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
  428. p_32 = (u32 *) ddr[i];
  429. if (p_32[k]) {
  430. printf(" 0x%08x", p_32[k]);
  431. m++;
  432. } else
  433. puts(" ");
  434. }
  435. if (m)
  436. puts("\n");
  437. else
  438. puts("\r");
  439. }
  440. puts("\n");
  441. }
  442. /* invalid the TLBs for DDR and setup new ones to cover p_addr */
  443. static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
  444. {
  445. u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  446. unsigned long epn;
  447. u32 tsize, valid, ptr;
  448. int ddr_esel;
  449. clear_ddr_tlbs_phys(p_addr, size>>20);
  450. /* Setup new tlb to cover the physical address */
  451. setup_ddr_tlbs_phys(p_addr, size>>20);
  452. ptr = vstart;
  453. ddr_esel = find_tlb_idx((void *)ptr, 1);
  454. if (ddr_esel != -1) {
  455. read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
  456. } else {
  457. printf("TLB error in function %s\n", __func__);
  458. return -1;
  459. }
  460. return 0;
  461. }
  462. /*
  463. * slide the testing window up to test another area
  464. * for 32_bit system, the maximum testable memory is limited to
  465. * CONFIG_MAX_MEM_MAPPED
  466. */
  467. int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  468. {
  469. phys_addr_t test_cap, p_addr;
  470. phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
  471. #if !defined(CONFIG_PHYS_64BIT) || \
  472. !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
  473. (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
  474. test_cap = p_size;
  475. #else
  476. test_cap = gd->ram_size;
  477. #endif
  478. p_addr = (*vstart) + (*size) + (*phys_offset);
  479. if (p_addr < test_cap - 1) {
  480. p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
  481. if (reset_tlb(p_addr, p_size, phys_offset) == -1)
  482. return -1;
  483. *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  484. *size = (u32) p_size;
  485. printf("Testing 0x%08llx - 0x%08llx\n",
  486. (u64)(*vstart) + (*phys_offset),
  487. (u64)(*vstart) + (*phys_offset) + (*size) - 1);
  488. } else
  489. return 1;
  490. return 0;
  491. }
  492. /* initialization for testing area */
  493. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  494. {
  495. phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
  496. *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
  497. *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
  498. *phys_offset = 0;
  499. #if !defined(CONFIG_PHYS_64BIT) || \
  500. !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
  501. (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
  502. if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
  503. puts("Cannot test more than ");
  504. print_size(CONFIG_MAX_MEM_MAPPED,
  505. " without proper 36BIT support.\n");
  506. }
  507. #endif
  508. printf("Testing 0x%08llx - 0x%08llx\n",
  509. (u64)(*vstart) + (*phys_offset),
  510. (u64)(*vstart) + (*phys_offset) + (*size) - 1);
  511. return 0;
  512. }
  513. /* invalid TLBs for DDR and remap as normal after testing */
  514. int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  515. {
  516. unsigned long epn;
  517. u32 tsize, valid, ptr;
  518. phys_addr_t rpn = 0;
  519. int ddr_esel;
  520. /* disable the TLBs for this testing */
  521. ptr = *vstart;
  522. while (ptr < (*vstart) + (*size)) {
  523. ddr_esel = find_tlb_idx((void *)ptr, 1);
  524. if (ddr_esel != -1) {
  525. read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
  526. disable_tlb(ddr_esel);
  527. }
  528. ptr += TSIZE_TO_BYTES(tsize);
  529. }
  530. puts("Remap DDR ");
  531. setup_ddr_tlbs(gd->ram_size>>20);
  532. puts("\n");
  533. return 0;
  534. }
  535. void arch_memory_failure_handle(void)
  536. {
  537. dump_spd_ddr_reg();
  538. }
  539. #endif