pll_config.h 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384
  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /*
  3. * Altera SoCFPGA Clock and PLL configuration
  4. */
  5. #ifndef __SOCFPGA_PLL_CONFIG_H__
  6. #define __SOCFPGA_PLL_CONFIG_H__
  7. #define CONFIG_HPS_DBCTRL_STAYOSC1 1
  8. #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
  9. #define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
  10. #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
  11. #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
  12. #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
  13. #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
  14. #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
  15. #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
  16. #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
  17. #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
  18. #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
  19. #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
  20. #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
  21. #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
  22. #define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
  23. #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
  24. #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
  25. #define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
  26. #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
  27. #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
  28. #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
  29. #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
  30. #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
  31. #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
  32. #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
  33. #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
  34. #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
  35. #define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
  36. #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
  37. #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
  38. #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
  39. #define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
  40. #define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
  41. #define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
  42. #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
  43. #define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
  44. #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
  45. #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
  46. #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
  47. #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
  48. #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
  49. #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
  50. #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
  51. #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
  52. #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
  53. #define CONFIG_HPS_CLK_OSC1_HZ 25000000
  54. #define CONFIG_HPS_CLK_OSC2_HZ 25000000
  55. #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
  56. #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
  57. #define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
  58. #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
  59. #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
  60. #define CONFIG_HPS_CLK_EMAC0_HZ 250000000
  61. #define CONFIG_HPS_CLK_EMAC1_HZ 1953125
  62. #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
  63. #define CONFIG_HPS_CLK_NAND_HZ 50000000
  64. #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
  65. #define CONFIG_HPS_CLK_QSPI_HZ 3125000
  66. #define CONFIG_HPS_CLK_SPIM_HZ 200000000
  67. #define CONFIG_HPS_CLK_CAN0_HZ 100000000
  68. #define CONFIG_HPS_CLK_CAN1_HZ 100000000
  69. #define CONFIG_HPS_CLK_GPIODB_HZ 32000
  70. #define CONFIG_HPS_CLK_L4_MP_HZ 100000000
  71. #define CONFIG_HPS_CLK_L4_SP_HZ 100000000
  72. #define CONFIG_HPS_ALTERAGRP_MPUCLK 1
  73. #define CONFIG_HPS_ALTERAGRP_MAINCLK 3
  74. #define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
  75. #endif /* __SOCFPGA_PLL_CONFIG_H__ */