Kconfig 5.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175
  1. if ARCH_SOCFPGA
  2. config NR_DRAM_BANKS
  3. default 1
  4. config SPL_STACK_R_ADDR
  5. default 0x00800000 if TARGET_SOCFPGA_GEN5
  6. config SPL_SYS_MALLOC_F_LEN
  7. default 0x800 if TARGET_SOCFPGA_GEN5
  8. config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  9. default 0xa2
  10. config SYS_MALLOC_F_LEN
  11. default 0x2000 if TARGET_SOCFPGA_ARRIA10
  12. default 0x2000 if TARGET_SOCFPGA_GEN5
  13. config SYS_TEXT_BASE
  14. default 0x01000040 if TARGET_SOCFPGA_ARRIA10
  15. default 0x01000040 if TARGET_SOCFPGA_GEN5
  16. config TARGET_SOCFPGA_ARRIA5
  17. bool
  18. select TARGET_SOCFPGA_GEN5
  19. config TARGET_SOCFPGA_ARRIA10
  20. bool
  21. select SPL_ALTERA_SDRAM
  22. select SPL_BOARD_INIT if SPL
  23. select CLK
  24. select SPL_CLK if SPL
  25. select DM_I2C
  26. select DM_RESET
  27. select SPL_DM_RESET if SPL
  28. select REGMAP
  29. select SPL_REGMAP if SPL
  30. select SYSCON
  31. select SPL_SYSCON if SPL
  32. select ETH_DESIGNWARE_SOCFPGA
  33. imply FPGA_SOCFPGA
  34. imply USE_TINY_PRINTF
  35. config TARGET_SOCFPGA_CYCLONE5
  36. bool
  37. select TARGET_SOCFPGA_GEN5
  38. config TARGET_SOCFPGA_GEN5
  39. bool
  40. select SPL_ALTERA_SDRAM
  41. imply FPGA_SOCFPGA
  42. imply SPL_STACK_R
  43. imply SPL_SYS_MALLOC_SIMPLE
  44. imply USE_TINY_PRINTF
  45. config TARGET_SOCFPGA_STRATIX10
  46. bool
  47. select ARMV8_MULTIENTRY
  48. select ARMV8_SET_SMPEN
  49. select ARMV8_SPIN_TABLE
  50. select FPGA_STRATIX10
  51. choice
  52. prompt "Altera SOCFPGA board select"
  53. optional
  54. config TARGET_SOCFPGA_ARIES_MCVEVK
  55. bool "Aries MCVEVK (Cyclone V)"
  56. select TARGET_SOCFPGA_CYCLONE5
  57. config TARGET_SOCFPGA_ARRIA10_SOCDK
  58. bool "Altera SOCFPGA SoCDK (Arria 10)"
  59. select TARGET_SOCFPGA_ARRIA10
  60. config TARGET_SOCFPGA_ARRIA5_SOCDK
  61. bool "Altera SOCFPGA SoCDK (Arria V)"
  62. select TARGET_SOCFPGA_ARRIA5
  63. config TARGET_SOCFPGA_CYCLONE5_SOCDK
  64. bool "Altera SOCFPGA SoCDK (Cyclone V)"
  65. select TARGET_SOCFPGA_CYCLONE5
  66. config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  67. bool "Devboards DBM-SoC1 (Cyclone V)"
  68. select TARGET_SOCFPGA_CYCLONE5
  69. config TARGET_SOCFPGA_EBV_SOCRATES
  70. bool "EBV SoCrates (Cyclone V)"
  71. select TARGET_SOCFPGA_CYCLONE5
  72. config TARGET_SOCFPGA_IS1
  73. bool "IS1 (Cyclone V)"
  74. select TARGET_SOCFPGA_CYCLONE5
  75. config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  76. bool "samtec VIN|ING FPGA (Cyclone V)"
  77. select BOARD_LATE_INIT
  78. select TARGET_SOCFPGA_CYCLONE5
  79. config TARGET_SOCFPGA_SR1500
  80. bool "SR1500 (Cyclone V)"
  81. select TARGET_SOCFPGA_CYCLONE5
  82. config TARGET_SOCFPGA_STRATIX10_SOCDK
  83. bool "Intel SOCFPGA SoCDK (Stratix 10)"
  84. select TARGET_SOCFPGA_STRATIX10
  85. config TARGET_SOCFPGA_TERASIC_DE0_NANO
  86. bool "Terasic DE0-Nano-Atlas (Cyclone V)"
  87. select TARGET_SOCFPGA_CYCLONE5
  88. config TARGET_SOCFPGA_TERASIC_DE10_NANO
  89. bool "Terasic DE10-Nano (Cyclone V)"
  90. select TARGET_SOCFPGA_CYCLONE5
  91. config TARGET_SOCFPGA_TERASIC_DE1_SOC
  92. bool "Terasic DE1-SoC (Cyclone V)"
  93. select TARGET_SOCFPGA_CYCLONE5
  94. config TARGET_SOCFPGA_TERASIC_SOCKIT
  95. bool "Terasic SoCkit (Cyclone V)"
  96. select TARGET_SOCFPGA_CYCLONE5
  97. endchoice
  98. config SYS_BOARD
  99. default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  100. default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
  101. default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  102. default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  103. default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  104. default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  105. default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  106. default "is1" if TARGET_SOCFPGA_IS1
  107. default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
  108. default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  109. default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  110. default "sr1500" if TARGET_SOCFPGA_SR1500
  111. default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
  112. default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  113. config SYS_VENDOR
  114. default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
  115. default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
  116. default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  117. default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
  118. default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
  119. default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  120. default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
  121. default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  122. default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  123. default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  124. default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  125. default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
  126. config SYS_SOC
  127. default "socfpga"
  128. config SYS_CONFIG_NAME
  129. default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  130. default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
  131. default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  132. default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  133. default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  134. default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
  135. default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
  136. default "socfpga_is1" if TARGET_SOCFPGA_IS1
  137. default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
  138. default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  139. default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  140. default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
  141. default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
  142. default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  143. endif