amlogic,meson-gxbb-reset.h 4.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2. /*
  3. * Copyright (c) 2016 BayLibre, SAS.
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
  7. #define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
  8. /* RESET0 */
  9. #define RESET_HIU 0
  10. /* 1 */
  11. #define RESET_DOS_RESET 2
  12. #define RESET_DDR_TOP 3
  13. #define RESET_DCU_RESET 4
  14. #define RESET_VIU 5
  15. #define RESET_AIU 6
  16. #define RESET_VID_PLL_DIV 7
  17. /* 8 */
  18. #define RESET_PMUX 9
  19. #define RESET_VENC 10
  20. #define RESET_ASSIST 11
  21. #define RESET_AFIFO2 12
  22. #define RESET_VCBUS 13
  23. /* 14 */
  24. /* 15 */
  25. #define RESET_GIC 16
  26. #define RESET_CAPB3_DECODE 17
  27. #define RESET_NAND_CAPB3 18
  28. #define RESET_HDMITX_CAPB3 19
  29. #define RESET_MALI_CAPB3 20
  30. #define RESET_DOS_CAPB3 21
  31. #define RESET_SYS_CPU_CAPB3 22
  32. #define RESET_CBUS_CAPB3 23
  33. #define RESET_AHB_CNTL 24
  34. #define RESET_AHB_DATA 25
  35. #define RESET_VCBUS_CLK81 26
  36. #define RESET_MMC 27
  37. #define RESET_MIPI_0 28
  38. #define RESET_MIPI_1 29
  39. #define RESET_MIPI_2 30
  40. #define RESET_MIPI_3 31
  41. /* RESET1 */
  42. #define RESET_CPPM 32
  43. #define RESET_DEMUX 33
  44. #define RESET_USB_OTG 34
  45. #define RESET_DDR 35
  46. #define RESET_AO_RESET 36
  47. #define RESET_BT656 37
  48. #define RESET_AHB_SRAM 38
  49. /* 39 */
  50. #define RESET_PARSER 40
  51. #define RESET_BLKMV 41
  52. #define RESET_ISA 42
  53. #define RESET_ETHERNET 43
  54. #define RESET_SD_EMMC_A 44
  55. #define RESET_SD_EMMC_B 45
  56. #define RESET_SD_EMMC_C 46
  57. #define RESET_ROM_BOOT 47
  58. #define RESET_SYS_CPU_0 48
  59. #define RESET_SYS_CPU_1 49
  60. #define RESET_SYS_CPU_2 50
  61. #define RESET_SYS_CPU_3 51
  62. #define RESET_SYS_CPU_CORE_0 52
  63. #define RESET_SYS_CPU_CORE_1 53
  64. #define RESET_SYS_CPU_CORE_2 54
  65. #define RESET_SYS_CPU_CORE_3 55
  66. #define RESET_SYS_PLL_DIV 56
  67. #define RESET_SYS_CPU_AXI 57
  68. #define RESET_SYS_CPU_L2 58
  69. #define RESET_SYS_CPU_P 59
  70. #define RESET_SYS_CPU_MBIST 60
  71. #define RESET_ACODEC 61
  72. /* 62 */
  73. /* 63 */
  74. /* RESET2 */
  75. #define RESET_VD_RMEM 64
  76. #define RESET_AUDIN 65
  77. #define RESET_HDMI_TX 66
  78. /* 67 */
  79. /* 68 */
  80. /* 69 */
  81. #define RESET_GE2D 70
  82. #define RESET_PARSER_REG 71
  83. #define RESET_PARSER_FETCH 72
  84. #define RESET_PARSER_CTL 73
  85. #define RESET_PARSER_TOP 74
  86. /* 75 */
  87. /* 76 */
  88. #define RESET_AO_CPU_RESET 77
  89. #define RESET_MALI 78
  90. #define RESET_HDMI_SYSTEM_RESET 79
  91. /* 80-95 */
  92. /* RESET3 */
  93. #define RESET_RING_OSCILLATOR 96
  94. #define RESET_SYS_CPU 97
  95. #define RESET_EFUSE 98
  96. #define RESET_SYS_CPU_BVCI 99
  97. #define RESET_AIFIFO 100
  98. #define RESET_TVFE 101
  99. #define RESET_AHB_BRIDGE_CNTL 102
  100. /* 103 */
  101. #define RESET_AUDIO_DAC 104
  102. #define RESET_DEMUX_TOP 105
  103. #define RESET_DEMUX_DES 106
  104. #define RESET_DEMUX_S2P_0 107
  105. #define RESET_DEMUX_S2P_1 108
  106. #define RESET_DEMUX_RESET_0 109
  107. #define RESET_DEMUX_RESET_1 110
  108. #define RESET_DEMUX_RESET_2 111
  109. /* 112-127 */
  110. /* RESET4 */
  111. /* 128 */
  112. /* 129 */
  113. /* 130 */
  114. /* 131 */
  115. #define RESET_DVIN_RESET 132
  116. #define RESET_RDMA 133
  117. #define RESET_VENCI 134
  118. #define RESET_VENCP 135
  119. /* 136 */
  120. #define RESET_VDAC 137
  121. #define RESET_RTC 138
  122. /* 139 */
  123. #define RESET_VDI6 140
  124. #define RESET_VENCL 141
  125. #define RESET_I2C_MASTER_2 142
  126. #define RESET_I2C_MASTER_1 143
  127. /* 144-159 */
  128. /* RESET5 */
  129. /* 160-191 */
  130. /* RESET6 */
  131. #define RESET_PERIPHS_GENERAL 192
  132. #define RESET_PERIPHS_SPICC 193
  133. #define RESET_PERIPHS_SMART_CARD 194
  134. #define RESET_PERIPHS_SAR_ADC 195
  135. #define RESET_PERIPHS_I2C_MASTER_0 196
  136. #define RESET_SANA 197
  137. /* 198 */
  138. #define RESET_PERIPHS_STREAM_INTERFACE 199
  139. #define RESET_PERIPHS_SDIO 200
  140. #define RESET_PERIPHS_UART_0 201
  141. #define RESET_PERIPHS_UART_1_2 202
  142. #define RESET_PERIPHS_ASYNC_0 203
  143. #define RESET_PERIPHS_ASYNC_1 204
  144. #define RESET_PERIPHS_SPI_0 205
  145. #define RESET_PERIPHS_SDHC 206
  146. #define RESET_UART_SLIP 207
  147. /* 208-223 */
  148. /* RESET7 */
  149. #define RESET_USB_DDR_0 224
  150. #define RESET_USB_DDR_1 225
  151. #define RESET_USB_DDR_2 226
  152. #define RESET_USB_DDR_3 227
  153. /* 228 */
  154. #define RESET_DEVICE_MMC_ARB 229
  155. /* 230 */
  156. #define RESET_VID_LOCK 231
  157. #define RESET_A9_DMC_PIPEL 232
  158. /* 233-255 */
  159. #endif