xlnx-zynqmp-clk.h 2.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Xilinx Zynq MPSoC Firmware layer
  4. *
  5. * Copyright (C) 2014-2018 Xilinx, Inc.
  6. *
  7. */
  8. #ifndef _DT_BINDINGS_CLK_ZYNQMP_H
  9. #define _DT_BINDINGS_CLK_ZYNQMP_H
  10. #define IOPLL 0
  11. #define RPLL 1
  12. #define APLL 2
  13. #define DPLL 3
  14. #define VPLL 4
  15. #define IOPLL_TO_FPD 5
  16. #define RPLL_TO_FPD 6
  17. #define APLL_TO_LPD 7
  18. #define DPLL_TO_LPD 8
  19. #define VPLL_TO_LPD 9
  20. #define ACPU 10
  21. #define ACPU_HALF 11
  22. #define DBF_FPD 12
  23. #define DBF_LPD 13
  24. #define DBG_TRACE 14
  25. #define DBG_TSTMP 15
  26. #define DP_VIDEO_REF 16
  27. #define DP_AUDIO_REF 17
  28. #define DP_STC_REF 18
  29. #define GDMA_REF 19
  30. #define DPDMA_REF 20
  31. #define DDR_REF 21
  32. #define SATA_REF 22
  33. #define PCIE_REF 23
  34. #define GPU_REF 24
  35. #define GPU_PP0_REF 25
  36. #define GPU_PP1_REF 26
  37. #define TOPSW_MAIN 27
  38. #define TOPSW_LSBUS 28
  39. #define GTGREF0_REF 29
  40. #define LPD_SWITCH 30
  41. #define LPD_LSBUS 31
  42. #define USB0_BUS_REF 32
  43. #define USB1_BUS_REF 33
  44. #define USB3_DUAL_REF 34
  45. #define USB0 35
  46. #define USB1 36
  47. #define CPU_R5 37
  48. #define CPU_R5_CORE 38
  49. #define CSU_SPB 39
  50. #define CSU_PLL 40
  51. #define PCAP 41
  52. #define IOU_SWITCH 42
  53. #define GEM_TSU_REF 43
  54. #define GEM_TSU 44
  55. #define GEM0_TX 45
  56. #define GEM1_TX 46
  57. #define GEM2_TX 47
  58. #define GEM3_TX 48
  59. #define GEM0_RX 49
  60. #define GEM1_RX 50
  61. #define GEM2_RX 51
  62. #define GEM3_RX 52
  63. #define QSPI_REF 53
  64. #define SDIO0_REF 54
  65. #define SDIO1_REF 55
  66. #define UART0_REF 56
  67. #define UART1_REF 57
  68. #define SPI0_REF 58
  69. #define SPI1_REF 59
  70. #define NAND_REF 60
  71. #define I2C0_REF 61
  72. #define I2C1_REF 62
  73. #define CAN0_REF 63
  74. #define CAN1_REF 64
  75. #define CAN0 65
  76. #define CAN1 66
  77. #define DLL_REF 67
  78. #define ADMA_REF 68
  79. #define TIMESTAMP_REF 69
  80. #define AMS_REF 70
  81. #define PL0_REF 71
  82. #define PL1_REF 72
  83. #define PL2_REF 73
  84. #define PL3_REF 74
  85. #define WDT 75
  86. #define IOPLL_INT 76
  87. #define IOPLL_PRE_SRC 77
  88. #define IOPLL_HALF 78
  89. #define IOPLL_INT_MUX 79
  90. #define IOPLL_POST_SRC 80
  91. #define RPLL_INT 81
  92. #define RPLL_PRE_SRC 82
  93. #define RPLL_HALF 83
  94. #define RPLL_INT_MUX 84
  95. #define RPLL_POST_SRC 85
  96. #define APLL_INT 86
  97. #define APLL_PRE_SRC 87
  98. #define APLL_HALF 88
  99. #define APLL_INT_MUX 89
  100. #define APLL_POST_SRC 90
  101. #define DPLL_INT 91
  102. #define DPLL_PRE_SRC 92
  103. #define DPLL_HALF 93
  104. #define DPLL_INT_MUX 94
  105. #define DPLL_POST_SRC 95
  106. #define VPLL_INT 96
  107. #define VPLL_PRE_SRC 97
  108. #define VPLL_HALF 98
  109. #define VPLL_INT_MUX 99
  110. #define VPLL_POST_SRC 100
  111. #define CAN0_MIO 101
  112. #define CAN1_MIO 102
  113. #define ACPU_FULL 103
  114. #define GEM0_REF 104
  115. #define GEM1_REF 105
  116. #define GEM2_REF 106
  117. #define GEM3_REF 107
  118. #define GEM0_REF_UNG 108
  119. #define GEM1_REF_UNG 109
  120. #define GEM2_REF_UNG 110
  121. #define GEM3_REF_UNG 111
  122. #define LPD_WDT 112
  123. #endif