tegra30-car.h 7.0 KB

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  1. /*
  2. * This header provides constants for binding nvidia,tegra30-car.
  3. *
  4. * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
  5. * registers. These IDs often match those in the CAR's RST_DEVICES registers,
  6. * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
  7. * this case, those clocks are assigned IDs above 160 in order to highlight
  8. * this issue. Implementations that interpret these clock IDs as bit values
  9. * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
  10. * explicitly handle these special cases.
  11. *
  12. * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
  13. * above.
  14. */
  15. #ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
  16. #define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
  17. #define TEGRA30_CLK_CPU 0
  18. /* 1 */
  19. /* 2 */
  20. /* 3 */
  21. #define TEGRA30_CLK_RTC 4
  22. #define TEGRA30_CLK_TIMER 5
  23. #define TEGRA30_CLK_UARTA 6
  24. /* 7 (register bit affects uartb and vfir) */
  25. #define TEGRA30_CLK_GPIO 8
  26. #define TEGRA30_CLK_SDMMC2 9
  27. /* 10 (register bit affects spdif_in and spdif_out) */
  28. #define TEGRA30_CLK_I2S1 11
  29. #define TEGRA30_CLK_I2C1 12
  30. #define TEGRA30_CLK_NDFLASH 13
  31. #define TEGRA30_CLK_SDMMC1 14
  32. #define TEGRA30_CLK_SDMMC4 15
  33. /* 16 */
  34. #define TEGRA30_CLK_PWM 17
  35. #define TEGRA30_CLK_I2S2 18
  36. #define TEGRA30_CLK_EPP 19
  37. /* 20 (register bit affects vi and vi_sensor) */
  38. #define TEGRA30_CLK_GR2D 21
  39. #define TEGRA30_CLK_USBD 22
  40. #define TEGRA30_CLK_ISP 23
  41. #define TEGRA30_CLK_GR3D 24
  42. /* 25 */
  43. #define TEGRA30_CLK_DISP2 26
  44. #define TEGRA30_CLK_DISP1 27
  45. #define TEGRA30_CLK_HOST1X 28
  46. #define TEGRA30_CLK_VCP 29
  47. #define TEGRA30_CLK_I2S0 30
  48. #define TEGRA30_CLK_COP_CACHE 31
  49. #define TEGRA30_CLK_MC 32
  50. #define TEGRA30_CLK_AHBDMA 33
  51. #define TEGRA30_CLK_APBDMA 34
  52. /* 35 */
  53. #define TEGRA30_CLK_KBC 36
  54. #define TEGRA30_CLK_STATMON 37
  55. #define TEGRA30_CLK_PMC 38
  56. /* 39 (register bit affects fuse and fuse_burn) */
  57. #define TEGRA30_CLK_KFUSE 40
  58. #define TEGRA30_CLK_SBC1 41
  59. #define TEGRA30_CLK_NOR 42
  60. /* 43 */
  61. #define TEGRA30_CLK_SBC2 44
  62. /* 45 */
  63. #define TEGRA30_CLK_SBC3 46
  64. #define TEGRA30_CLK_I2C5 47
  65. #define TEGRA30_CLK_DSIA 48
  66. /* 49 (register bit affects cve and tvo) */
  67. #define TEGRA30_CLK_MIPI 50
  68. #define TEGRA30_CLK_HDMI 51
  69. #define TEGRA30_CLK_CSI 52
  70. #define TEGRA30_CLK_TVDAC 53
  71. #define TEGRA30_CLK_I2C2 54
  72. #define TEGRA30_CLK_UARTC 55
  73. /* 56 */
  74. #define TEGRA30_CLK_EMC 57
  75. #define TEGRA30_CLK_USB2 58
  76. #define TEGRA30_CLK_USB3 59
  77. #define TEGRA30_CLK_MPE 60
  78. #define TEGRA30_CLK_VDE 61
  79. #define TEGRA30_CLK_BSEA 62
  80. #define TEGRA30_CLK_BSEV 63
  81. #define TEGRA30_CLK_SPEEDO 64
  82. #define TEGRA30_CLK_UARTD 65
  83. #define TEGRA30_CLK_UARTE 66
  84. #define TEGRA30_CLK_I2C3 67
  85. #define TEGRA30_CLK_SBC4 68
  86. #define TEGRA30_CLK_SDMMC3 69
  87. #define TEGRA30_CLK_PCIE 70
  88. #define TEGRA30_CLK_OWR 71
  89. #define TEGRA30_CLK_AFI 72
  90. #define TEGRA30_CLK_CSITE 73
  91. /* 74 */
  92. #define TEGRA30_CLK_AVPUCQ 75
  93. #define TEGRA30_CLK_LA 76
  94. /* 77 */
  95. /* 78 */
  96. #define TEGRA30_CLK_DTV 79
  97. #define TEGRA30_CLK_NDSPEED 80
  98. #define TEGRA30_CLK_I2CSLOW 81
  99. #define TEGRA30_CLK_DSIB 82
  100. /* 83 */
  101. #define TEGRA30_CLK_IRAMA 84
  102. #define TEGRA30_CLK_IRAMB 85
  103. #define TEGRA30_CLK_IRAMC 86
  104. #define TEGRA30_CLK_IRAMD 87
  105. #define TEGRA30_CLK_CRAM2 88
  106. /* 89 */
  107. #define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
  108. /* 91 */
  109. #define TEGRA30_CLK_CSUS 92
  110. #define TEGRA30_CLK_CDEV2 93
  111. #define TEGRA30_CLK_CDEV1 94
  112. /* 95 */
  113. #define TEGRA30_CLK_CPU_G 96
  114. #define TEGRA30_CLK_CPU_LP 97
  115. #define TEGRA30_CLK_GR3D2 98
  116. #define TEGRA30_CLK_MSELECT 99
  117. #define TEGRA30_CLK_TSENSOR 100
  118. #define TEGRA30_CLK_I2S3 101
  119. #define TEGRA30_CLK_I2S4 102
  120. #define TEGRA30_CLK_I2C4 103
  121. #define TEGRA30_CLK_SBC5 104
  122. #define TEGRA30_CLK_SBC6 105
  123. #define TEGRA30_CLK_D_AUDIO 106
  124. #define TEGRA30_CLK_APBIF 107
  125. #define TEGRA30_CLK_DAM0 108
  126. #define TEGRA30_CLK_DAM1 109
  127. #define TEGRA30_CLK_DAM2 110
  128. #define TEGRA30_CLK_HDA2CODEC_2X 111
  129. #define TEGRA30_CLK_ATOMICS 112
  130. #define TEGRA30_CLK_AUDIO0_2X 113
  131. #define TEGRA30_CLK_AUDIO1_2X 114
  132. #define TEGRA30_CLK_AUDIO2_2X 115
  133. #define TEGRA30_CLK_AUDIO3_2X 116
  134. #define TEGRA30_CLK_AUDIO4_2X 117
  135. #define TEGRA30_CLK_SPDIF_2X 118
  136. #define TEGRA30_CLK_ACTMON 119
  137. #define TEGRA30_CLK_EXTERN1 120
  138. #define TEGRA30_CLK_EXTERN2 121
  139. #define TEGRA30_CLK_EXTERN3 122
  140. #define TEGRA30_CLK_SATA_OOB 123
  141. #define TEGRA30_CLK_SATA 124
  142. #define TEGRA30_CLK_HDA 125
  143. /* 126 */
  144. #define TEGRA30_CLK_SE 127
  145. #define TEGRA30_CLK_HDA2HDMI 128
  146. #define TEGRA30_CLK_SATA_COLD 129
  147. /* 130 */
  148. /* 131 */
  149. /* 132 */
  150. /* 133 */
  151. /* 134 */
  152. /* 135 */
  153. /* 136 */
  154. /* 137 */
  155. /* 138 */
  156. /* 139 */
  157. /* 140 */
  158. /* 141 */
  159. /* 142 */
  160. /* 143 */
  161. /* 144 */
  162. /* 145 */
  163. /* 146 */
  164. /* 147 */
  165. /* 148 */
  166. /* 149 */
  167. /* 150 */
  168. /* 151 */
  169. /* 152 */
  170. /* 153 */
  171. /* 154 */
  172. /* 155 */
  173. /* 156 */
  174. /* 157 */
  175. /* 158 */
  176. /* 159 */
  177. #define TEGRA30_CLK_UARTB 160
  178. #define TEGRA30_CLK_VFIR 161
  179. #define TEGRA30_CLK_SPDIF_IN 162
  180. #define TEGRA30_CLK_SPDIF_OUT 163
  181. #define TEGRA30_CLK_VI 164
  182. #define TEGRA30_CLK_VI_SENSOR 165
  183. #define TEGRA30_CLK_FUSE 166
  184. #define TEGRA30_CLK_FUSE_BURN 167
  185. #define TEGRA30_CLK_CVE 168
  186. #define TEGRA30_CLK_TVO 169
  187. #define TEGRA30_CLK_CLK_32K 170
  188. #define TEGRA30_CLK_CLK_M 171
  189. #define TEGRA30_CLK_CLK_M_DIV2 172
  190. #define TEGRA30_CLK_CLK_M_DIV4 173
  191. #define TEGRA30_CLK_PLL_REF 174
  192. #define TEGRA30_CLK_PLL_C 175
  193. #define TEGRA30_CLK_PLL_C_OUT1 176
  194. #define TEGRA30_CLK_PLL_M 177
  195. #define TEGRA30_CLK_PLL_M_OUT1 178
  196. #define TEGRA30_CLK_PLL_P 179
  197. #define TEGRA30_CLK_PLL_P_OUT1 180
  198. #define TEGRA30_CLK_PLL_P_OUT2 181
  199. #define TEGRA30_CLK_PLL_P_OUT3 182
  200. #define TEGRA30_CLK_PLL_P_OUT4 183
  201. #define TEGRA30_CLK_PLL_A 184
  202. #define TEGRA30_CLK_PLL_A_OUT0 185
  203. #define TEGRA30_CLK_PLL_D 186
  204. #define TEGRA30_CLK_PLL_D_OUT0 187
  205. #define TEGRA30_CLK_PLL_D2 188
  206. #define TEGRA30_CLK_PLL_D2_OUT0 189
  207. #define TEGRA30_CLK_PLL_U 190
  208. #define TEGRA30_CLK_PLL_X 191
  209. #define TEGRA30_CLK_PLL_X_OUT0 192
  210. #define TEGRA30_CLK_PLL_E 193
  211. #define TEGRA30_CLK_SPDIF_IN_SYNC 194
  212. #define TEGRA30_CLK_I2S0_SYNC 195
  213. #define TEGRA30_CLK_I2S1_SYNC 196
  214. #define TEGRA30_CLK_I2S2_SYNC 197
  215. #define TEGRA30_CLK_I2S3_SYNC 198
  216. #define TEGRA30_CLK_I2S4_SYNC 199
  217. #define TEGRA30_CLK_VIMCLK_SYNC 200
  218. #define TEGRA30_CLK_AUDIO0 201
  219. #define TEGRA30_CLK_AUDIO1 202
  220. #define TEGRA30_CLK_AUDIO2 203
  221. #define TEGRA30_CLK_AUDIO3 204
  222. #define TEGRA30_CLK_AUDIO4 205
  223. #define TEGRA30_CLK_SPDIF 206
  224. #define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
  225. #define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
  226. #define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
  227. #define TEGRA30_CLK_SCLK 210
  228. #define TEGRA30_CLK_BLINK 211
  229. #define TEGRA30_CLK_CCLK_G 212
  230. #define TEGRA30_CLK_CCLK_LP 213
  231. #define TEGRA30_CLK_TWD 214
  232. #define TEGRA30_CLK_CML0 215
  233. #define TEGRA30_CLK_CML1 216
  234. #define TEGRA30_CLK_HCLK 217
  235. #define TEGRA30_CLK_PCLK 218
  236. /* 219 */
  237. /* 220 */
  238. /* 221 */
  239. /* 222 */
  240. /* 223 */
  241. /* 288 */
  242. /* 289 */
  243. /* 290 */
  244. /* 291 */
  245. /* 292 */
  246. /* 293 */
  247. /* 294 */
  248. /* 295 */
  249. /* 296 */
  250. /* 297 */
  251. /* 298 */
  252. /* 299 */
  253. #define TEGRA30_CLK_CLK_OUT_1_MUX 300
  254. #define TEGRA30_CLK_CLK_OUT_2_MUX 301
  255. #define TEGRA30_CLK_CLK_OUT_3_MUX 302
  256. #define TEGRA30_CLK_AUDIO0_MUX 303
  257. #define TEGRA30_CLK_AUDIO1_MUX 304
  258. #define TEGRA30_CLK_AUDIO2_MUX 305
  259. #define TEGRA30_CLK_AUDIO3_MUX 306
  260. #define TEGRA30_CLK_AUDIO4_MUX 307
  261. #define TEGRA30_CLK_SPDIF_MUX 308
  262. #define TEGRA30_CLK_CLK_MAX 309
  263. #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */