sun50i-h6-ccu.h 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125
  1. // SPDX-License-Identifier: (GPL-2.0+ or MIT)
  2. /*
  3. * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
  4. */
  5. #ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
  6. #define _DT_BINDINGS_CLK_SUN50I_H6_H_
  7. #define CLK_PLL_PERIPH0 3
  8. #define CLK_CPUX 21
  9. #define CLK_APB1 26
  10. #define CLK_DE 29
  11. #define CLK_BUS_DE 30
  12. #define CLK_DEINTERLACE 31
  13. #define CLK_BUS_DEINTERLACE 32
  14. #define CLK_GPU 33
  15. #define CLK_BUS_GPU 34
  16. #define CLK_CE 35
  17. #define CLK_BUS_CE 36
  18. #define CLK_VE 37
  19. #define CLK_BUS_VE 38
  20. #define CLK_EMCE 39
  21. #define CLK_BUS_EMCE 40
  22. #define CLK_VP9 41
  23. #define CLK_BUS_VP9 42
  24. #define CLK_BUS_DMA 43
  25. #define CLK_BUS_MSGBOX 44
  26. #define CLK_BUS_SPINLOCK 45
  27. #define CLK_BUS_HSTIMER 46
  28. #define CLK_AVS 47
  29. #define CLK_BUS_DBG 48
  30. #define CLK_BUS_PSI 49
  31. #define CLK_BUS_PWM 50
  32. #define CLK_BUS_IOMMU 51
  33. #define CLK_MBUS_DMA 53
  34. #define CLK_MBUS_VE 54
  35. #define CLK_MBUS_CE 55
  36. #define CLK_MBUS_TS 56
  37. #define CLK_MBUS_NAND 57
  38. #define CLK_MBUS_CSI 58
  39. #define CLK_MBUS_DEINTERLACE 59
  40. #define CLK_NAND0 61
  41. #define CLK_NAND1 62
  42. #define CLK_BUS_NAND 63
  43. #define CLK_MMC0 64
  44. #define CLK_MMC1 65
  45. #define CLK_MMC2 66
  46. #define CLK_BUS_MMC0 67
  47. #define CLK_BUS_MMC1 68
  48. #define CLK_BUS_MMC2 69
  49. #define CLK_BUS_UART0 70
  50. #define CLK_BUS_UART1 71
  51. #define CLK_BUS_UART2 72
  52. #define CLK_BUS_UART3 73
  53. #define CLK_BUS_I2C0 74
  54. #define CLK_BUS_I2C1 75
  55. #define CLK_BUS_I2C2 76
  56. #define CLK_BUS_I2C3 77
  57. #define CLK_BUS_SCR0 78
  58. #define CLK_BUS_SCR1 79
  59. #define CLK_SPI0 80
  60. #define CLK_SPI1 81
  61. #define CLK_BUS_SPI0 82
  62. #define CLK_BUS_SPI1 83
  63. #define CLK_BUS_EMAC 84
  64. #define CLK_TS 85
  65. #define CLK_BUS_TS 86
  66. #define CLK_IR_TX 87
  67. #define CLK_BUS_IR_TX 88
  68. #define CLK_BUS_THS 89
  69. #define CLK_I2S3 90
  70. #define CLK_I2S0 91
  71. #define CLK_I2S1 92
  72. #define CLK_I2S2 93
  73. #define CLK_BUS_I2S0 94
  74. #define CLK_BUS_I2S1 95
  75. #define CLK_BUS_I2S2 96
  76. #define CLK_BUS_I2S3 97
  77. #define CLK_SPDIF 98
  78. #define CLK_BUS_SPDIF 99
  79. #define CLK_DMIC 100
  80. #define CLK_BUS_DMIC 101
  81. #define CLK_AUDIO_HUB 102
  82. #define CLK_BUS_AUDIO_HUB 103
  83. #define CLK_USB_OHCI0 104
  84. #define CLK_USB_PHY0 105
  85. #define CLK_USB_PHY1 106
  86. #define CLK_USB_OHCI3 107
  87. #define CLK_USB_PHY3 108
  88. #define CLK_USB_HSIC_12M 109
  89. #define CLK_USB_HSIC 110
  90. #define CLK_BUS_OHCI0 111
  91. #define CLK_BUS_OHCI3 112
  92. #define CLK_BUS_EHCI0 113
  93. #define CLK_BUS_XHCI 114
  94. #define CLK_BUS_EHCI3 115
  95. #define CLK_BUS_OTG 116
  96. #define CLK_PCIE_REF_100M 117
  97. #define CLK_PCIE_REF 118
  98. #define CLK_PCIE_REF_OUT 119
  99. #define CLK_PCIE_MAXI 120
  100. #define CLK_PCIE_AUX 121
  101. #define CLK_BUS_PCIE 122
  102. #define CLK_HDMI 123
  103. #define CLK_HDMI_SLOW 124
  104. #define CLK_HDMI_CEC 125
  105. #define CLK_BUS_HDMI 126
  106. #define CLK_BUS_TCON_TOP 127
  107. #define CLK_TCON_LCD0 128
  108. #define CLK_BUS_TCON_LCD0 129
  109. #define CLK_TCON_TV0 130
  110. #define CLK_BUS_TCON_TV0 131
  111. #define CLK_CSI_CCI 132
  112. #define CLK_CSI_TOP 133
  113. #define CLK_CSI_MCLK 134
  114. #define CLK_BUS_CSI 135
  115. #define CLK_HDCP 136
  116. #define CLK_BUS_HDCP 137
  117. #endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */