stm32mp1-clksrc.h 8.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. *
  5. */
  6. #ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
  7. #define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
  8. /* PLL output is enable when x=1, with x=p,q or r */
  9. #define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
  10. /* st,clksrc: mandatory clock source */
  11. #define CLK_MPU_HSI 0x00000200
  12. #define CLK_MPU_HSE 0x00000201
  13. #define CLK_MPU_PLL1P 0x00000202
  14. #define CLK_MPU_PLL1P_DIV 0x00000203
  15. #define CLK_AXI_HSI 0x00000240
  16. #define CLK_AXI_HSE 0x00000241
  17. #define CLK_AXI_PLL2P 0x00000242
  18. #define CLK_MCU_HSI 0x00000480
  19. #define CLK_MCU_HSE 0x00000481
  20. #define CLK_MCU_CSI 0x00000482
  21. #define CLK_MCU_PLL3P 0x00000483
  22. #define CLK_PLL12_HSI 0x00000280
  23. #define CLK_PLL12_HSE 0x00000281
  24. #define CLK_PLL3_HSI 0x00008200
  25. #define CLK_PLL3_HSE 0x00008201
  26. #define CLK_PLL3_CSI 0x00008202
  27. #define CLK_PLL4_HSI 0x00008240
  28. #define CLK_PLL4_HSE 0x00008241
  29. #define CLK_PLL4_CSI 0x00008242
  30. #define CLK_PLL4_I2SCKIN 0x00008243
  31. #define CLK_RTC_DISABLED 0x00001400
  32. #define CLK_RTC_LSE 0x00001401
  33. #define CLK_RTC_LSI 0x00001402
  34. #define CLK_RTC_HSE 0x00001403
  35. #define CLK_MCO1_HSI 0x00008000
  36. #define CLK_MCO1_HSE 0x00008001
  37. #define CLK_MCO1_CSI 0x00008002
  38. #define CLK_MCO1_LSI 0x00008003
  39. #define CLK_MCO1_LSE 0x00008004
  40. #define CLK_MCO1_DISABLED 0x0000800F
  41. #define CLK_MCO2_MPU 0x00008040
  42. #define CLK_MCO2_AXI 0x00008041
  43. #define CLK_MCO2_MCU 0x00008042
  44. #define CLK_MCO2_PLL4P 0x00008043
  45. #define CLK_MCO2_HSE 0x00008044
  46. #define CLK_MCO2_HSI 0x00008045
  47. #define CLK_MCO2_DISABLED 0x0000804F
  48. /* st,pkcs: peripheral kernel clock source */
  49. #define CLK_I2C12_PCLK1 0x00008C00
  50. #define CLK_I2C12_PLL4R 0x00008C01
  51. #define CLK_I2C12_HSI 0x00008C02
  52. #define CLK_I2C12_CSI 0x00008C03
  53. #define CLK_I2C12_DISABLED 0x00008C07
  54. #define CLK_I2C35_PCLK1 0x00008C40
  55. #define CLK_I2C35_PLL4R 0x00008C41
  56. #define CLK_I2C35_HSI 0x00008C42
  57. #define CLK_I2C35_CSI 0x00008C43
  58. #define CLK_I2C35_DISABLED 0x00008C47
  59. #define CLK_I2C46_PCLK5 0x00000C00
  60. #define CLK_I2C46_PLL3Q 0x00000C01
  61. #define CLK_I2C46_HSI 0x00000C02
  62. #define CLK_I2C46_CSI 0x00000C03
  63. #define CLK_I2C46_DISABLED 0x00000C07
  64. #define CLK_SAI1_PLL4Q 0x00008C80
  65. #define CLK_SAI1_PLL3Q 0x00008C81
  66. #define CLK_SAI1_I2SCKIN 0x00008C82
  67. #define CLK_SAI1_CKPER 0x00008C83
  68. #define CLK_SAI1_PLL3R 0x00008C84
  69. #define CLK_SAI1_DISABLED 0x00008C87
  70. #define CLK_SAI2_PLL4Q 0x00008CC0
  71. #define CLK_SAI2_PLL3Q 0x00008CC1
  72. #define CLK_SAI2_I2SCKIN 0x00008CC2
  73. #define CLK_SAI2_CKPER 0x00008CC3
  74. #define CLK_SAI2_SPDIF 0x00008CC4
  75. #define CLK_SAI2_PLL3R 0x00008CC5
  76. #define CLK_SAI2_DISABLED 0x00008CC7
  77. #define CLK_SAI3_PLL4Q 0x00008D00
  78. #define CLK_SAI3_PLL3Q 0x00008D01
  79. #define CLK_SAI3_I2SCKIN 0x00008D02
  80. #define CLK_SAI3_CKPER 0x00008D03
  81. #define CLK_SAI3_PLL3R 0x00008D04
  82. #define CLK_SAI3_DISABLED 0x00008D07
  83. #define CLK_SAI4_PLL4Q 0x00008D40
  84. #define CLK_SAI4_PLL3Q 0x00008D41
  85. #define CLK_SAI4_I2SCKIN 0x00008D42
  86. #define CLK_SAI4_CKPER 0x00008D43
  87. #define CLK_SAI4_PLL3R 0x00008D44
  88. #define CLK_SAI4_DISABLED 0x00008D47
  89. #define CLK_SPI2S1_PLL4P 0x00008D80
  90. #define CLK_SPI2S1_PLL3Q 0x00008D81
  91. #define CLK_SPI2S1_I2SCKIN 0x00008D82
  92. #define CLK_SPI2S1_CKPER 0x00008D83
  93. #define CLK_SPI2S1_PLL3R 0x00008D84
  94. #define CLK_SPI2S1_DISABLED 0x00008D87
  95. #define CLK_SPI2S23_PLL4P 0x00008DC0
  96. #define CLK_SPI2S23_PLL3Q 0x00008DC1
  97. #define CLK_SPI2S23_I2SCKIN 0x00008DC2
  98. #define CLK_SPI2S23_CKPER 0x00008DC3
  99. #define CLK_SPI2S23_PLL3R 0x00008DC4
  100. #define CLK_SPI2S23_DISABLED 0x00008DC7
  101. #define CLK_SPI45_PCLK2 0x00008E00
  102. #define CLK_SPI45_PLL4Q 0x00008E01
  103. #define CLK_SPI45_HSI 0x00008E02
  104. #define CLK_SPI45_CSI 0x00008E03
  105. #define CLK_SPI45_HSE 0x00008E04
  106. #define CLK_SPI45_DISABLED 0x00008E07
  107. #define CLK_SPI6_PCLK5 0x00000C40
  108. #define CLK_SPI6_PLL4Q 0x00000C41
  109. #define CLK_SPI6_HSI 0x00000C42
  110. #define CLK_SPI6_CSI 0x00000C43
  111. #define CLK_SPI6_HSE 0x00000C44
  112. #define CLK_SPI6_PLL3Q 0x00000C45
  113. #define CLK_SPI6_DISABLED 0x00000C47
  114. #define CLK_UART6_PCLK2 0x00008E40
  115. #define CLK_UART6_PLL4Q 0x00008E41
  116. #define CLK_UART6_HSI 0x00008E42
  117. #define CLK_UART6_CSI 0x00008E43
  118. #define CLK_UART6_HSE 0x00008E44
  119. #define CLK_UART6_DISABLED 0x00008E47
  120. #define CLK_UART24_PCLK1 0x00008E80
  121. #define CLK_UART24_PLL4Q 0x00008E81
  122. #define CLK_UART24_HSI 0x00008E82
  123. #define CLK_UART24_CSI 0x00008E83
  124. #define CLK_UART24_HSE 0x00008E84
  125. #define CLK_UART24_DISABLED 0x00008E87
  126. #define CLK_UART35_PCLK1 0x00008EC0
  127. #define CLK_UART35_PLL4Q 0x00008EC1
  128. #define CLK_UART35_HSI 0x00008EC2
  129. #define CLK_UART35_CSI 0x00008EC3
  130. #define CLK_UART35_HSE 0x00008EC4
  131. #define CLK_UART35_DISABLED 0x00008EC7
  132. #define CLK_UART78_PCLK1 0x00008F00
  133. #define CLK_UART78_PLL4Q 0x00008F01
  134. #define CLK_UART78_HSI 0x00008F02
  135. #define CLK_UART78_CSI 0x00008F03
  136. #define CLK_UART78_HSE 0x00008F04
  137. #define CLK_UART78_DISABLED 0x00008F07
  138. #define CLK_UART1_PCLK5 0x00000C80
  139. #define CLK_UART1_PLL3Q 0x00000C81
  140. #define CLK_UART1_HSI 0x00000C82
  141. #define CLK_UART1_CSI 0x00000C83
  142. #define CLK_UART1_PLL4Q 0x00000C84
  143. #define CLK_UART1_HSE 0x00000C85
  144. #define CLK_UART1_DISABLED 0x00000C87
  145. #define CLK_SDMMC12_HCLK6 0x00008F40
  146. #define CLK_SDMMC12_PLL3R 0x00008F41
  147. #define CLK_SDMMC12_PLL4P 0x00008F42
  148. #define CLK_SDMMC12_HSI 0x00008F43
  149. #define CLK_SDMMC12_DISABLED 0x00008F47
  150. #define CLK_SDMMC3_HCLK2 0x00008F80
  151. #define CLK_SDMMC3_PLL3R 0x00008F81
  152. #define CLK_SDMMC3_PLL4P 0x00008F82
  153. #define CLK_SDMMC3_HSI 0x00008F83
  154. #define CLK_SDMMC3_DISABLED 0x00008F87
  155. #define CLK_ETH_PLL4P 0x00008FC0
  156. #define CLK_ETH_PLL3Q 0x00008FC1
  157. #define CLK_ETH_DISABLED 0x00008FC3
  158. #define CLK_QSPI_ACLK 0x00009000
  159. #define CLK_QSPI_PLL3R 0x00009001
  160. #define CLK_QSPI_PLL4P 0x00009002
  161. #define CLK_QSPI_CKPER 0x00009003
  162. #define CLK_FMC_ACLK 0x00009040
  163. #define CLK_FMC_PLL3R 0x00009041
  164. #define CLK_FMC_PLL4P 0x00009042
  165. #define CLK_FMC_CKPER 0x00009043
  166. #define CLK_FDCAN_HSE 0x000090C0
  167. #define CLK_FDCAN_PLL3Q 0x000090C1
  168. #define CLK_FDCAN_PLL4Q 0x000090C2
  169. #define CLK_FDCAN_PLL4R 0x000090C3
  170. #define CLK_SPDIF_PLL4P 0x00009140
  171. #define CLK_SPDIF_PLL3Q 0x00009141
  172. #define CLK_SPDIF_HSI 0x00009142
  173. #define CLK_SPDIF_DISABLED 0x00009143
  174. #define CLK_CEC_LSE 0x00009180
  175. #define CLK_CEC_LSI 0x00009181
  176. #define CLK_CEC_CSI_DIV122 0x00009182
  177. #define CLK_CEC_DISABLED 0x00009183
  178. #define CLK_USBPHY_HSE 0x000091C0
  179. #define CLK_USBPHY_PLL4R 0x000091C1
  180. #define CLK_USBPHY_HSE_DIV2 0x000091C2
  181. #define CLK_USBPHY_DISABLED 0x000091C3
  182. #define CLK_USBO_PLL4R 0x800091C0
  183. #define CLK_USBO_USBPHY 0x800091C1
  184. #define CLK_RNG1_CSI 0x00000CC0
  185. #define CLK_RNG1_PLL4R 0x00000CC1
  186. #define CLK_RNG1_LSE 0x00000CC2
  187. #define CLK_RNG1_LSI 0x00000CC3
  188. #define CLK_RNG2_CSI 0x00009200
  189. #define CLK_RNG2_PLL4R 0x00009201
  190. #define CLK_RNG2_LSE 0x00009202
  191. #define CLK_RNG2_LSI 0x00009203
  192. #define CLK_CKPER_HSI 0x00000D00
  193. #define CLK_CKPER_CSI 0x00000D01
  194. #define CLK_CKPER_HSE 0x00000D02
  195. #define CLK_CKPER_DISABLED 0x00000D03
  196. #define CLK_STGEN_HSI 0x00000D40
  197. #define CLK_STGEN_HSE 0x00000D41
  198. #define CLK_STGEN_DISABLED 0x00000D43
  199. #define CLK_DSI_DSIPLL 0x00009240
  200. #define CLK_DSI_PLL4P 0x00009241
  201. #define CLK_ADC_PLL4R 0x00009280
  202. #define CLK_ADC_CKPER 0x00009281
  203. #define CLK_ADC_PLL3Q 0x00009282
  204. #define CLK_ADC_DISABLED 0x00009283
  205. #define CLK_LPTIM45_PCLK3 0x000092C0
  206. #define CLK_LPTIM45_PLL4P 0x000092C1
  207. #define CLK_LPTIM45_PLL3Q 0x000092C2
  208. #define CLK_LPTIM45_LSE 0x000092C3
  209. #define CLK_LPTIM45_LSI 0x000092C4
  210. #define CLK_LPTIM45_CKPER 0x000092C5
  211. #define CLK_LPTIM45_DISABLED 0x000092C7
  212. #define CLK_LPTIM23_PCLK3 0x00009300
  213. #define CLK_LPTIM23_PLL4Q 0x00009301
  214. #define CLK_LPTIM23_CKPER 0x00009302
  215. #define CLK_LPTIM23_LSE 0x00009303
  216. #define CLK_LPTIM23_LSI 0x00009304
  217. #define CLK_LPTIM23_DISABLED 0x00009307
  218. #define CLK_LPTIM1_PCLK1 0x00009340
  219. #define CLK_LPTIM1_PLL4P 0x00009341
  220. #define CLK_LPTIM1_PLL3Q 0x00009342
  221. #define CLK_LPTIM1_LSE 0x00009343
  222. #define CLK_LPTIM1_LSI 0x00009344
  223. #define CLK_LPTIM1_CKPER 0x00009345
  224. #define CLK_LPTIM1_DISABLED 0x00009347
  225. /* define for st,pll /csg */
  226. #define SSCG_MODE_CENTER_SPREAD 0
  227. #define SSCG_MODE_DOWN_SPREAD 1
  228. /* define for st,drive */
  229. #define LSEDRV_LOWEST 0
  230. #define LSEDRV_MEDIUM_LOW 1
  231. #define LSEDRV_MEDIUM_HIGH 2
  232. #define LSEDRV_HIGHEST 3
  233. #endif