rk3399-cru.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
  4. */
  5. #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
  6. #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
  7. /* core clocks */
  8. #define PLL_APLLL 1
  9. #define PLL_APLLB 2
  10. #define PLL_DPLL 3
  11. #define PLL_CPLL 4
  12. #define PLL_GPLL 5
  13. #define PLL_NPLL 6
  14. #define PLL_VPLL 7
  15. #define ARMCLKL 8
  16. #define ARMCLKB 9
  17. /* sclk gates (special clocks) */
  18. #define SCLK_I2C1 65
  19. #define SCLK_I2C2 66
  20. #define SCLK_I2C3 67
  21. #define SCLK_I2C5 68
  22. #define SCLK_I2C6 69
  23. #define SCLK_I2C7 70
  24. #define SCLK_SPI0 71
  25. #define SCLK_SPI1 72
  26. #define SCLK_SPI2 73
  27. #define SCLK_SPI4 74
  28. #define SCLK_SPI5 75
  29. #define SCLK_SDMMC 76
  30. #define SCLK_SDIO 77
  31. #define SCLK_EMMC 78
  32. #define SCLK_TSADC 79
  33. #define SCLK_SARADC 80
  34. #define SCLK_UART0 81
  35. #define SCLK_UART1 82
  36. #define SCLK_UART2 83
  37. #define SCLK_UART3 84
  38. #define SCLK_SPDIF_8CH 85
  39. #define SCLK_I2S0_8CH 86
  40. #define SCLK_I2S1_8CH 87
  41. #define SCLK_I2S2_8CH 88
  42. #define SCLK_I2S_8CH_OUT 89
  43. #define SCLK_TIMER00 90
  44. #define SCLK_TIMER01 91
  45. #define SCLK_TIMER02 92
  46. #define SCLK_TIMER03 93
  47. #define SCLK_TIMER04 94
  48. #define SCLK_TIMER05 95
  49. #define SCLK_TIMER06 96
  50. #define SCLK_TIMER07 97
  51. #define SCLK_TIMER08 98
  52. #define SCLK_TIMER09 99
  53. #define SCLK_TIMER10 100
  54. #define SCLK_TIMER11 101
  55. #define SCLK_MACREF 102
  56. #define SCLK_MAC_RX 103
  57. #define SCLK_MAC_TX 104
  58. #define SCLK_MAC 105
  59. #define SCLK_MACREF_OUT 106
  60. #define SCLK_VOP0_PWM 107
  61. #define SCLK_VOP1_PWM 108
  62. #define SCLK_RGA_CORE 109
  63. #define SCLK_ISP0 110
  64. #define SCLK_ISP1 111
  65. #define SCLK_HDMI_CEC 112
  66. #define SCLK_HDMI_SFR 113
  67. #define SCLK_DP_CORE 114
  68. #define SCLK_PVTM_CORE_L 115
  69. #define SCLK_PVTM_CORE_B 116
  70. #define SCLK_PVTM_GPU 117
  71. #define SCLK_PVTM_DDR 118
  72. #define SCLK_MIPIDPHY_REF 119
  73. #define SCLK_MIPIDPHY_CFG 120
  74. #define SCLK_HSICPHY 121
  75. #define SCLK_USBPHY480M 122
  76. #define SCLK_USB2PHY0_REF 123
  77. #define SCLK_USB2PHY1_REF 124
  78. #define SCLK_UPHY0_TCPDPHY_REF 125
  79. #define SCLK_UPHY0_TCPDCORE 126
  80. #define SCLK_UPHY1_TCPDPHY_REF 127
  81. #define SCLK_UPHY1_TCPDCORE 128
  82. #define SCLK_USB3OTG0_REF 129
  83. #define SCLK_USB3OTG1_REF 130
  84. #define SCLK_USB3OTG0_SUSPEND 131
  85. #define SCLK_USB3OTG1_SUSPEND 132
  86. #define SCLK_CRYPTO0 133
  87. #define SCLK_CRYPTO1 134
  88. #define SCLK_CCI_TRACE 135
  89. #define SCLK_CS 136
  90. #define SCLK_CIF_OUT 137
  91. #define SCLK_PCIEPHY_REF 138
  92. #define SCLK_PCIE_CORE 139
  93. #define SCLK_M0_PERILP 140
  94. #define SCLK_M0_PERILP_DEC 141
  95. #define SCLK_CM0S 142
  96. #define SCLK_DBG_NOC 143
  97. #define SCLK_DBG_PD_CORE_B 144
  98. #define SCLK_DBG_PD_CORE_L 145
  99. #define SCLK_DFIMON0_TIMER 146
  100. #define SCLK_DFIMON1_TIMER 147
  101. #define SCLK_INTMEM0 148
  102. #define SCLK_INTMEM1 149
  103. #define SCLK_INTMEM2 150
  104. #define SCLK_INTMEM3 151
  105. #define SCLK_INTMEM4 152
  106. #define SCLK_INTMEM5 153
  107. #define SCLK_SDMMC_DRV 154
  108. #define SCLK_SDMMC_SAMPLE 155
  109. #define SCLK_SDIO_DRV 156
  110. #define SCLK_SDIO_SAMPLE 157
  111. #define SCLK_VDU_CORE 158
  112. #define SCLK_VDU_CA 159
  113. #define SCLK_PCIE_PM 160
  114. #define SCLK_SPDIF_REC_DPTX 161
  115. #define SCLK_DPHY_PLL 162
  116. #define SCLK_DPHY_TX0_CFG 163
  117. #define SCLK_DPHY_TX1RX1_CFG 164
  118. #define SCLK_DPHY_RX0_CFG 165
  119. #define SCLK_RMII_SRC 166
  120. #define SCLK_PCIEPHY_REF100M 167
  121. #define SCLK_USBPHY0_480M_SRC 168
  122. #define SCLK_USBPHY1_480M_SRC 169
  123. #define SCLK_DDRCLK 170
  124. #define SCLK_TESTOUT2 171
  125. #define DCLK_VOP0 180
  126. #define DCLK_VOP1 181
  127. #define DCLK_VOP0_DIV 182
  128. #define DCLK_VOP1_DIV 183
  129. #define DCLK_M0_PERILP 184
  130. #define FCLK_CM0S 190
  131. /* aclk gates */
  132. #define ACLK_PERIHP 192
  133. #define ACLK_PERIHP_NOC 193
  134. #define ACLK_PERILP0 194
  135. #define ACLK_PERILP0_NOC 195
  136. #define ACLK_PERF_PCIE 196
  137. #define ACLK_PCIE 197
  138. #define ACLK_INTMEM 198
  139. #define ACLK_TZMA 199
  140. #define ACLK_DCF 200
  141. #define ACLK_CCI 201
  142. #define ACLK_CCI_NOC0 202
  143. #define ACLK_CCI_NOC1 203
  144. #define ACLK_CCI_GRF 204
  145. #define ACLK_CENTER 205
  146. #define ACLK_CENTER_MAIN_NOC 206
  147. #define ACLK_CENTER_PERI_NOC 207
  148. #define ACLK_GPU 208
  149. #define ACLK_PERF_GPU 209
  150. #define ACLK_GPU_GRF 210
  151. #define ACLK_DMAC0_PERILP 211
  152. #define ACLK_DMAC1_PERILP 212
  153. #define ACLK_GMAC 213
  154. #define ACLK_GMAC_NOC 214
  155. #define ACLK_PERF_GMAC 215
  156. #define ACLK_VOP0_NOC 216
  157. #define ACLK_VOP0 217
  158. #define ACLK_VOP1_NOC 218
  159. #define ACLK_VOP1 219
  160. #define ACLK_RGA 220
  161. #define ACLK_RGA_NOC 221
  162. #define ACLK_HDCP 222
  163. #define ACLK_HDCP_NOC 223
  164. #define ACLK_HDCP22 224
  165. #define ACLK_IEP 225
  166. #define ACLK_IEP_NOC 226
  167. #define ACLK_VIO 227
  168. #define ACLK_VIO_NOC 228
  169. #define ACLK_ISP0 229
  170. #define ACLK_ISP1 230
  171. #define ACLK_ISP0_NOC 231
  172. #define ACLK_ISP1_NOC 232
  173. #define ACLK_ISP0_WRAPPER 233
  174. #define ACLK_ISP1_WRAPPER 234
  175. #define ACLK_VCODEC 235
  176. #define ACLK_VCODEC_NOC 236
  177. #define ACLK_VDU 237
  178. #define ACLK_VDU_NOC 238
  179. #define ACLK_PERI 239
  180. #define ACLK_EMMC 240
  181. #define ACLK_EMMC_CORE 241
  182. #define ACLK_EMMC_NOC 242
  183. #define ACLK_EMMC_GRF 243
  184. #define ACLK_USB3 244
  185. #define ACLK_USB3_NOC 245
  186. #define ACLK_USB3OTG0 246
  187. #define ACLK_USB3OTG1 247
  188. #define ACLK_USB3_RKSOC_AXI_PERF 248
  189. #define ACLK_USB3_GRF 249
  190. #define ACLK_GIC 250
  191. #define ACLK_GIC_NOC 251
  192. #define ACLK_GIC_ADB400_CORE_L_2_GIC 252
  193. #define ACLK_GIC_ADB400_CORE_B_2_GIC 253
  194. #define ACLK_GIC_ADB400_GIC_2_CORE_L 254
  195. #define ACLK_GIC_ADB400_GIC_2_CORE_B 255
  196. #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
  197. #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
  198. #define ACLK_ADB400M_PD_CORE_L 258
  199. #define ACLK_ADB400M_PD_CORE_B 259
  200. #define ACLK_PERF_CORE_L 260
  201. #define ACLK_PERF_CORE_B 261
  202. #define ACLK_GIC_PRE 262
  203. #define ACLK_VOP0_PRE 263
  204. #define ACLK_VOP1_PRE 264
  205. /* pclk gates */
  206. #define PCLK_PERIHP 320
  207. #define PCLK_PERIHP_NOC 321
  208. #define PCLK_PERILP0 322
  209. #define PCLK_PERILP1 323
  210. #define PCLK_PERILP1_NOC 324
  211. #define PCLK_PERILP_SGRF 325
  212. #define PCLK_PERIHP_GRF 326
  213. #define PCLK_PCIE 327
  214. #define PCLK_SGRF 328
  215. #define PCLK_INTR_ARB 329
  216. #define PCLK_CENTER_MAIN_NOC 330
  217. #define PCLK_CIC 331
  218. #define PCLK_COREDBG_B 332
  219. #define PCLK_COREDBG_L 333
  220. #define PCLK_DBG_CXCS_PD_CORE_B 334
  221. #define PCLK_DCF 335
  222. #define PCLK_GPIO2 336
  223. #define PCLK_GPIO3 337
  224. #define PCLK_GPIO4 338
  225. #define PCLK_GRF 339
  226. #define PCLK_HSICPHY 340
  227. #define PCLK_I2C1 341
  228. #define PCLK_I2C2 342
  229. #define PCLK_I2C3 343
  230. #define PCLK_I2C5 344
  231. #define PCLK_I2C6 345
  232. #define PCLK_I2C7 346
  233. #define PCLK_SPI0 347
  234. #define PCLK_SPI1 348
  235. #define PCLK_SPI2 349
  236. #define PCLK_SPI4 350
  237. #define PCLK_SPI5 351
  238. #define PCLK_UART0 352
  239. #define PCLK_UART1 353
  240. #define PCLK_UART2 354
  241. #define PCLK_UART3 355
  242. #define PCLK_TSADC 356
  243. #define PCLK_SARADC 357
  244. #define PCLK_GMAC 358
  245. #define PCLK_GMAC_NOC 359
  246. #define PCLK_TIMER0 360
  247. #define PCLK_TIMER1 361
  248. #define PCLK_EDP 362
  249. #define PCLK_EDP_NOC 363
  250. #define PCLK_EDP_CTRL 364
  251. #define PCLK_VIO 365
  252. #define PCLK_VIO_NOC 366
  253. #define PCLK_VIO_GRF 367
  254. #define PCLK_MIPI_DSI0 368
  255. #define PCLK_MIPI_DSI1 369
  256. #define PCLK_HDCP 370
  257. #define PCLK_HDCP_NOC 371
  258. #define PCLK_HDMI_CTRL 372
  259. #define PCLK_DP_CTRL 373
  260. #define PCLK_HDCP22 374
  261. #define PCLK_GASKET 375
  262. #define PCLK_DDR 376
  263. #define PCLK_DDR_MON 377
  264. #define PCLK_DDR_SGRF 378
  265. #define PCLK_ISP1_WRAPPER 379
  266. #define PCLK_WDT 380
  267. #define PCLK_EFUSE1024NS 381
  268. #define PCLK_EFUSE1024S 382
  269. #define PCLK_PMU_INTR_ARB 383
  270. #define PCLK_MAILBOX0 384
  271. #define PCLK_USBPHY_MUX_G 385
  272. #define PCLK_UPHY0_TCPHY_G 386
  273. #define PCLK_UPHY0_TCPD_G 387
  274. #define PCLK_UPHY1_TCPHY_G 388
  275. #define PCLK_UPHY1_TCPD_G 389
  276. #define PCLK_ALIVE 390
  277. /* hclk gates */
  278. #define HCLK_PERIHP 448
  279. #define HCLK_PERILP0 449
  280. #define HCLK_PERILP1 450
  281. #define HCLK_PERILP0_NOC 451
  282. #define HCLK_PERILP1_NOC 452
  283. #define HCLK_M0_PERILP 453
  284. #define HCLK_M0_PERILP_NOC 454
  285. #define HCLK_AHB1TOM 455
  286. #define HCLK_HOST0 456
  287. #define HCLK_HOST0_ARB 457
  288. #define HCLK_HOST1 458
  289. #define HCLK_HOST1_ARB 459
  290. #define HCLK_HSIC 460
  291. #define HCLK_SD 461
  292. #define HCLK_SDMMC 462
  293. #define HCLK_SDMMC_NOC 463
  294. #define HCLK_M_CRYPTO0 464
  295. #define HCLK_M_CRYPTO1 465
  296. #define HCLK_S_CRYPTO0 466
  297. #define HCLK_S_CRYPTO1 467
  298. #define HCLK_I2S0_8CH 468
  299. #define HCLK_I2S1_8CH 469
  300. #define HCLK_I2S2_8CH 470
  301. #define HCLK_SPDIF 471
  302. #define HCLK_VOP0_NOC 472
  303. #define HCLK_VOP0 473
  304. #define HCLK_VOP1_NOC 474
  305. #define HCLK_VOP1 475
  306. #define HCLK_ROM 476
  307. #define HCLK_IEP 477
  308. #define HCLK_IEP_NOC 478
  309. #define HCLK_ISP0 479
  310. #define HCLK_ISP1 480
  311. #define HCLK_ISP0_NOC 481
  312. #define HCLK_ISP1_NOC 482
  313. #define HCLK_ISP0_WRAPPER 483
  314. #define HCLK_ISP1_WRAPPER 484
  315. #define HCLK_RGA 485
  316. #define HCLK_RGA_NOC 486
  317. #define HCLK_HDCP 487
  318. #define HCLK_HDCP_NOC 488
  319. #define HCLK_HDCP22 489
  320. #define HCLK_VCODEC 490
  321. #define HCLK_VCODEC_NOC 491
  322. #define HCLK_VDU 492
  323. #define HCLK_VDU_NOC 493
  324. #define HCLK_SDIO 494
  325. #define HCLK_SDIO_NOC 495
  326. #define HCLK_SDIOAUDIO_NOC 496
  327. #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
  328. /* pmu-clocks indices */
  329. #define PLL_PPLL 1
  330. #define SCLK_32K_SUSPEND_PMU 2
  331. #define SCLK_SPI3_PMU 3
  332. #define SCLK_TIMER12_PMU 4
  333. #define SCLK_TIMER13_PMU 5
  334. #define SCLK_UART4_PMU 6
  335. #define SCLK_PVTM_PMU 7
  336. #define SCLK_WIFI_PMU 8
  337. #define SCLK_I2C0_PMU 9
  338. #define SCLK_I2C4_PMU 10
  339. #define SCLK_I2C8_PMU 11
  340. #define PCLK_SRC_PMU 19
  341. #define PCLK_PMU 20
  342. #define PCLK_PMUGRF_PMU 21
  343. #define PCLK_INTMEM1_PMU 22
  344. #define PCLK_GPIO0_PMU 23
  345. #define PCLK_GPIO1_PMU 24
  346. #define PCLK_SGRF_PMU 25
  347. #define PCLK_NOC_PMU 26
  348. #define PCLK_I2C0_PMU 27
  349. #define PCLK_I2C4_PMU 28
  350. #define PCLK_I2C8_PMU 29
  351. #define PCLK_RKPWM_PMU 30
  352. #define PCLK_SPI3_PMU 31
  353. #define PCLK_TIMER_PMU 32
  354. #define PCLK_MAILBOX_PMU 33
  355. #define PCLK_UART4_PMU 34
  356. #define PCLK_WDT_M0_PMU 35
  357. #define FCLK_CM0S_SRC_PMU 44
  358. #define FCLK_CM0S_PMU 45
  359. #define SCLK_CM0S_PMU 46
  360. #define HCLK_CM0S_PMU 47
  361. #define DCLK_CM0S_PMU 48
  362. #define PCLK_INTR_ARB_PMU 49
  363. #define HCLK_NOC_PMU 50
  364. #define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
  365. /* soft-reset indices */
  366. /* cru_softrst_con0 */
  367. #define SRST_CORE_L0 0
  368. #define SRST_CORE_B0 1
  369. #define SRST_CORE_PO_L0 2
  370. #define SRST_CORE_PO_B0 3
  371. #define SRST_L2_L 4
  372. #define SRST_L2_B 5
  373. #define SRST_ADB_L 6
  374. #define SRST_ADB_B 7
  375. #define SRST_A_CCI 8
  376. #define SRST_A_CCIM0_NOC 9
  377. #define SRST_A_CCIM1_NOC 10
  378. #define SRST_DBG_NOC 11
  379. /* cru_softrst_con1 */
  380. #define SRST_CORE_L0_T 16
  381. #define SRST_CORE_L1 17
  382. #define SRST_CORE_L2 18
  383. #define SRST_CORE_L3 19
  384. #define SRST_CORE_PO_L0_T 20
  385. #define SRST_CORE_PO_L1 21
  386. #define SRST_CORE_PO_L2 22
  387. #define SRST_CORE_PO_L3 23
  388. #define SRST_A_ADB400_GIC2COREL 24
  389. #define SRST_A_ADB400_COREL2GIC 25
  390. #define SRST_P_DBG_L 26
  391. #define SRST_L2_L_T 28
  392. #define SRST_ADB_L_T 29
  393. #define SRST_A_RKPERF_L 30
  394. #define SRST_PVTM_CORE_L 31
  395. /* cru_softrst_con2 */
  396. #define SRST_CORE_B0_T 32
  397. #define SRST_CORE_B1 33
  398. #define SRST_CORE_PO_B0_T 36
  399. #define SRST_CORE_PO_B1 37
  400. #define SRST_A_ADB400_GIC2COREB 40
  401. #define SRST_A_ADB400_COREB2GIC 41
  402. #define SRST_P_DBG_B 42
  403. #define SRST_L2_B_T 43
  404. #define SRST_ADB_B_T 45
  405. #define SRST_A_RKPERF_B 46
  406. #define SRST_PVTM_CORE_B 47
  407. /* cru_softrst_con3 */
  408. #define SRST_A_CCI_T 50
  409. #define SRST_A_CCIM0_NOC_T 51
  410. #define SRST_A_CCIM1_NOC_T 52
  411. #define SRST_A_ADB400M_PD_CORE_B_T 53
  412. #define SRST_A_ADB400M_PD_CORE_L_T 54
  413. #define SRST_DBG_NOC_T 55
  414. #define SRST_DBG_CXCS 56
  415. #define SRST_CCI_TRACE 57
  416. #define SRST_P_CCI_GRF 58
  417. /* cru_softrst_con4 */
  418. #define SRST_A_CENTER_MAIN_NOC 64
  419. #define SRST_A_CENTER_PERI_NOC 65
  420. #define SRST_P_CENTER_MAIN 66
  421. #define SRST_P_DDRMON 67
  422. #define SRST_P_CIC 68
  423. #define SRST_P_CENTER_SGRF 69
  424. #define SRST_DDR0_MSCH 70
  425. #define SRST_DDRCFG0_MSCH 71
  426. #define SRST_DDR0 72
  427. #define SRST_DDRPHY0 73
  428. #define SRST_DDR1_MSCH 74
  429. #define SRST_DDRCFG1_MSCH 75
  430. #define SRST_DDR1 76
  431. #define SRST_DDRPHY1 77
  432. #define SRST_DDR_CIC 78
  433. #define SRST_PVTM_DDR 79
  434. /* cru_softrst_con5 */
  435. #define SRST_A_VCODEC_NOC 80
  436. #define SRST_A_VCODEC 81
  437. #define SRST_H_VCODEC_NOC 82
  438. #define SRST_H_VCODEC 83
  439. #define SRST_A_VDU_NOC 88
  440. #define SRST_A_VDU 89
  441. #define SRST_H_VDU_NOC 90
  442. #define SRST_H_VDU 91
  443. #define SRST_VDU_CORE 92
  444. #define SRST_VDU_CA 93
  445. /* cru_softrst_con6 */
  446. #define SRST_A_IEP_NOC 96
  447. #define SRST_A_VOP_IEP 97
  448. #define SRST_A_IEP 98
  449. #define SRST_H_IEP_NOC 99
  450. #define SRST_H_IEP 100
  451. #define SRST_A_RGA_NOC 102
  452. #define SRST_A_RGA 103
  453. #define SRST_H_RGA_NOC 104
  454. #define SRST_H_RGA 105
  455. #define SRST_RGA_CORE 106
  456. #define SRST_EMMC_NOC 108
  457. #define SRST_EMMC 109
  458. #define SRST_EMMC_GRF 110
  459. /* cru_softrst_con7 */
  460. #define SRST_A_PERIHP_NOC 112
  461. #define SRST_P_PERIHP_GRF 113
  462. #define SRST_H_PERIHP_NOC 114
  463. #define SRST_USBHOST0 115
  464. #define SRST_HOSTC0_AUX 116
  465. #define SRST_HOST0_ARB 117
  466. #define SRST_USBHOST1 118
  467. #define SRST_HOSTC1_AUX 119
  468. #define SRST_HOST1_ARB 120
  469. #define SRST_SDIO0 121
  470. #define SRST_SDMMC 122
  471. #define SRST_HSIC 123
  472. #define SRST_HSIC_AUX 124
  473. #define SRST_AHB1TOM 125
  474. #define SRST_P_PERIHP_NOC 126
  475. #define SRST_HSICPHY 127
  476. /* cru_softrst_con8 */
  477. #define SRST_A_PCIE 128
  478. #define SRST_P_PCIE 129
  479. #define SRST_PCIE_CORE 130
  480. #define SRST_PCIE_MGMT 131
  481. #define SRST_PCIE_MGMT_STICKY 132
  482. #define SRST_PCIE_PIPE 133
  483. #define SRST_PCIE_PM 134
  484. #define SRST_PCIEPHY 135
  485. #define SRST_A_GMAC_NOC 136
  486. #define SRST_A_GMAC 137
  487. #define SRST_P_GMAC_NOC 138
  488. #define SRST_P_GMAC_GRF 140
  489. #define SRST_HSICPHY_POR 142
  490. #define SRST_HSICPHY_UTMI 143
  491. /* cru_softrst_con9 */
  492. #define SRST_USB2PHY0_POR 144
  493. #define SRST_USB2PHY0_UTMI_PORT0 145
  494. #define SRST_USB2PHY0_UTMI_PORT1 146
  495. #define SRST_USB2PHY0_EHCIPHY 147
  496. #define SRST_UPHY0_PIPE_L00 148
  497. #define SRST_UPHY0 149
  498. #define SRST_UPHY0_TCPDPWRUP 150
  499. #define SRST_USB2PHY1_POR 152
  500. #define SRST_USB2PHY1_UTMI_PORT0 153
  501. #define SRST_USB2PHY1_UTMI_PORT1 154
  502. #define SRST_USB2PHY1_EHCIPHY 155
  503. #define SRST_UPHY1_PIPE_L00 156
  504. #define SRST_UPHY1 157
  505. #define SRST_UPHY1_TCPDPWRUP 158
  506. /* cru_softrst_con10 */
  507. #define SRST_A_PERILP0_NOC 160
  508. #define SRST_A_DCF 161
  509. #define SRST_GIC500 162
  510. #define SRST_DMAC0_PERILP0 163
  511. #define SRST_DMAC1_PERILP0 164
  512. #define SRST_TZMA 165
  513. #define SRST_INTMEM 166
  514. #define SRST_ADB400_MST0 167
  515. #define SRST_ADB400_MST1 168
  516. #define SRST_ADB400_SLV0 169
  517. #define SRST_ADB400_SLV1 170
  518. #define SRST_H_PERILP0 171
  519. #define SRST_H_PERILP0_NOC 172
  520. #define SRST_ROM 173
  521. #define SRST_CRYPTO_S 174
  522. #define SRST_CRYPTO_M 175
  523. /* cru_softrst_con11 */
  524. #define SRST_P_DCF 176
  525. #define SRST_CM0S_NOC 177
  526. #define SRST_CM0S 178
  527. #define SRST_CM0S_DBG 179
  528. #define SRST_CM0S_PO 180
  529. #define SRST_CRYPTO 181
  530. #define SRST_P_PERILP1_SGRF 182
  531. #define SRST_P_PERILP1_GRF 183
  532. #define SRST_CRYPTO1_S 184
  533. #define SRST_CRYPTO1_M 185
  534. #define SRST_CRYPTO1 186
  535. #define SRST_GIC_NOC 188
  536. #define SRST_SD_NOC 189
  537. #define SRST_SDIOAUDIO_BRG 190
  538. /* cru_softrst_con12 */
  539. #define SRST_H_PERILP1 192
  540. #define SRST_H_PERILP1_NOC 193
  541. #define SRST_H_I2S0_8CH 194
  542. #define SRST_H_I2S1_8CH 195
  543. #define SRST_H_I2S2_8CH 196
  544. #define SRST_H_SPDIF_8CH 197
  545. #define SRST_P_PERILP1_NOC 198
  546. #define SRST_P_EFUSE_1024 199
  547. #define SRST_P_EFUSE_1024S 200
  548. #define SRST_P_I2C0 201
  549. #define SRST_P_I2C1 202
  550. #define SRST_P_I2C2 203
  551. #define SRST_P_I2C3 204
  552. #define SRST_P_I2C4 205
  553. #define SRST_P_I2C5 206
  554. #define SRST_P_MAILBOX0 207
  555. /* cru_softrst_con13 */
  556. #define SRST_P_UART0 208
  557. #define SRST_P_UART1 209
  558. #define SRST_P_UART2 210
  559. #define SRST_P_UART3 211
  560. #define SRST_P_SARADC 212
  561. #define SRST_P_TSADC 213
  562. #define SRST_P_SPI0 214
  563. #define SRST_P_SPI1 215
  564. #define SRST_P_SPI2 216
  565. #define SRST_P_SPI4 217
  566. #define SRST_P_SPI5 218
  567. #define SRST_SPI0 219
  568. #define SRST_SPI1 220
  569. #define SRST_SPI2 221
  570. #define SRST_SPI4 222
  571. #define SRST_SPI5 223
  572. /* cru_softrst_con14 */
  573. #define SRST_I2S0_8CH 224
  574. #define SRST_I2S1_8CH 225
  575. #define SRST_I2S2_8CH 226
  576. #define SRST_SPDIF_8CH 227
  577. #define SRST_UART0 228
  578. #define SRST_UART1 229
  579. #define SRST_UART2 230
  580. #define SRST_UART3 231
  581. #define SRST_TSADC 232
  582. #define SRST_I2C0 233
  583. #define SRST_I2C1 234
  584. #define SRST_I2C2 235
  585. #define SRST_I2C3 236
  586. #define SRST_I2C4 237
  587. #define SRST_I2C5 238
  588. #define SRST_SDIOAUDIO_NOC 239
  589. /* cru_softrst_con15 */
  590. #define SRST_A_VIO_NOC 240
  591. #define SRST_A_HDCP_NOC 241
  592. #define SRST_A_HDCP 242
  593. #define SRST_H_HDCP_NOC 243
  594. #define SRST_H_HDCP 244
  595. #define SRST_P_HDCP_NOC 245
  596. #define SRST_P_HDCP 246
  597. #define SRST_P_HDMI_CTRL 247
  598. #define SRST_P_DP_CTRL 248
  599. #define SRST_S_DP_CTRL 249
  600. #define SRST_C_DP_CTRL 250
  601. #define SRST_P_MIPI_DSI0 251
  602. #define SRST_P_MIPI_DSI1 252
  603. #define SRST_DP_CORE 253
  604. #define SRST_DP_I2S 254
  605. /* cru_softrst_con16 */
  606. #define SRST_GASKET 256
  607. #define SRST_VIO_GRF 258
  608. #define SRST_DPTX_SPDIF_REC 259
  609. #define SRST_HDMI_CTRL 260
  610. #define SRST_HDCP_CTRL 261
  611. #define SRST_A_ISP0_NOC 262
  612. #define SRST_A_ISP1_NOC 263
  613. #define SRST_H_ISP0_NOC 266
  614. #define SRST_H_ISP1_NOC 267
  615. #define SRST_H_ISP0 268
  616. #define SRST_H_ISP1 269
  617. #define SRST_ISP0 270
  618. #define SRST_ISP1 271
  619. /* cru_softrst_con17 */
  620. #define SRST_A_VOP0_NOC 272
  621. #define SRST_A_VOP1_NOC 273
  622. #define SRST_A_VOP0 274
  623. #define SRST_A_VOP1 275
  624. #define SRST_H_VOP0_NOC 276
  625. #define SRST_H_VOP1_NOC 277
  626. #define SRST_H_VOP0 278
  627. #define SRST_H_VOP1 279
  628. #define SRST_D_VOP0 280
  629. #define SRST_D_VOP1 281
  630. #define SRST_VOP0_PWM 282
  631. #define SRST_VOP1_PWM 283
  632. #define SRST_P_EDP_NOC 284
  633. #define SRST_P_EDP_CTRL 285
  634. /* cru_softrst_con18 */
  635. #define SRST_A_GPU 288
  636. #define SRST_A_GPU_NOC 289
  637. #define SRST_A_GPU_GRF 290
  638. #define SRST_PVTM_GPU 291
  639. #define SRST_A_USB3_NOC 292
  640. #define SRST_A_USB3_OTG0 293
  641. #define SRST_A_USB3_OTG1 294
  642. #define SRST_A_USB3_GRF 295
  643. #define SRST_PMU 296
  644. /* cru_softrst_con19 */
  645. #define SRST_P_TIMER0_5 304
  646. #define SRST_TIMER0 305
  647. #define SRST_TIMER1 306
  648. #define SRST_TIMER2 307
  649. #define SRST_TIMER3 308
  650. #define SRST_TIMER4 309
  651. #define SRST_TIMER5 310
  652. #define SRST_P_TIMER6_11 311
  653. #define SRST_TIMER6 312
  654. #define SRST_TIMER7 313
  655. #define SRST_TIMER8 314
  656. #define SRST_TIMER9 315
  657. #define SRST_TIMER10 316
  658. #define SRST_TIMER11 317
  659. #define SRST_P_INTR_ARB_PMU 318
  660. #define SRST_P_ALIVE_SGRF 319
  661. /* cru_softrst_con20 */
  662. #define SRST_P_GPIO2 320
  663. #define SRST_P_GPIO3 321
  664. #define SRST_P_GPIO4 322
  665. #define SRST_P_GRF 323
  666. #define SRST_P_ALIVE_NOC 324
  667. #define SRST_P_WDT0 325
  668. #define SRST_P_WDT1 326
  669. #define SRST_P_INTR_ARB 327
  670. #define SRST_P_UPHY0_DPTX 328
  671. #define SRST_P_UPHY0_APB 330
  672. #define SRST_P_UPHY0_TCPHY 332
  673. #define SRST_P_UPHY1_TCPHY 333
  674. #define SRST_P_UPHY0_TCPDCTRL 334
  675. #define SRST_P_UPHY1_TCPDCTRL 335
  676. /* pmu soft-reset indices */
  677. /* pmu_cru_softrst_con0 */
  678. #define SRST_P_NOC 0
  679. #define SRST_P_INTMEM 1
  680. #define SRST_H_CM0S 2
  681. #define SRST_H_CM0S_NOC 3
  682. #define SRST_DBG_CM0S 4
  683. #define SRST_PO_CM0S 5
  684. #define SRST_P_SPI3 6
  685. #define SRST_SPI3 7
  686. #define SRST_P_TIMER_0_1 8
  687. #define SRST_P_TIMER_0 9
  688. #define SRST_P_TIMER_1 10
  689. #define SRST_P_UART4 11
  690. #define SRST_UART4 12
  691. #define SRST_P_WDT 13
  692. /* pmu_cru_softrst_con1 */
  693. #define SRST_P_I2C6 16
  694. #define SRST_P_I2C7 17
  695. #define SRST_P_I2C8 18
  696. #define SRST_P_MAILBOX 19
  697. #define SRST_P_RKPWM 20
  698. #define SRST_P_PMUGRF 21
  699. #define SRST_P_SGRF 22
  700. #define SRST_P_GPIO0 23
  701. #define SRST_P_GPIO1 24
  702. #define SRST_P_CRU 25
  703. #define SRST_P_INTR 26
  704. #define SRST_PVTM 27
  705. #define SRST_I2C6 28
  706. #define SRST_I2C7 29
  707. #define SRST_I2C8 30
  708. #endif