rk3308-cru.h 9.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
  4. * Author: Finley Xiao <finley.xiao@rock-chips.com>
  5. */
  6. #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
  7. #define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H
  8. /* core clocks */
  9. #define PLL_APLL 1
  10. #define PLL_DPLL 2
  11. #define PLL_VPLL0 3
  12. #define PLL_VPLL1 4
  13. #define ARMCLK 5
  14. /* sclk (special clocks) */
  15. #define USB480M 14
  16. #define SCLK_RTC32K 15
  17. #define SCLK_PVTM_CORE 16
  18. #define SCLK_UART0 17
  19. #define SCLK_UART1 18
  20. #define SCLK_UART2 19
  21. #define SCLK_UART3 20
  22. #define SCLK_UART4 21
  23. #define SCLK_I2C0 22
  24. #define SCLK_I2C1 23
  25. #define SCLK_I2C2 24
  26. #define SCLK_I2C3 25
  27. #define SCLK_PWM0 26
  28. #define SCLK_SPI0 27
  29. #define SCLK_SPI1 28
  30. #define SCLK_SPI2 29
  31. #define SCLK_TIMER0 30
  32. #define SCLK_TIMER1 31
  33. #define SCLK_TIMER2 32
  34. #define SCLK_TIMER3 33
  35. #define SCLK_TIMER4 34
  36. #define SCLK_TIMER5 35
  37. #define SCLK_TSADC 36
  38. #define SCLK_SARADC 37
  39. #define SCLK_OTP 38
  40. #define SCLK_OTP_USR 39
  41. #define SCLK_CPU_BOOST 40
  42. #define SCLK_CRYPTO 41
  43. #define SCLK_CRYPTO_APK 42
  44. #define SCLK_NANDC_DIV 43
  45. #define SCLK_NANDC_DIV50 44
  46. #define SCLK_NANDC 45
  47. #define SCLK_SDMMC_DIV 46
  48. #define SCLK_SDMMC_DIV50 47
  49. #define SCLK_SDMMC 48
  50. #define SCLK_SDMMC_DRV 49
  51. #define SCLK_SDMMC_SAMPLE 50
  52. #define SCLK_SDIO_DIV 51
  53. #define SCLK_SDIO_DIV50 52
  54. #define SCLK_SDIO 53
  55. #define SCLK_SDIO_DRV 54
  56. #define SCLK_SDIO_SAMPLE 55
  57. #define SCLK_EMMC_DIV 56
  58. #define SCLK_EMMC_DIV50 57
  59. #define SCLK_EMMC 58
  60. #define SCLK_EMMC_DRV 59
  61. #define SCLK_EMMC_SAMPLE 60
  62. #define SCLK_SFC 61
  63. #define SCLK_OTG_ADP 62
  64. #define SCLK_MAC_SRC 63
  65. #define SCLK_MAC 64
  66. #define SCLK_MAC_REF 65
  67. #define SCLK_MAC_RX_TX 66
  68. #define SCLK_MAC_RMII 67
  69. #define SCLK_DDR_MON_TIMER 68
  70. #define SCLK_DDR_MON 69
  71. #define SCLK_DDRCLK 70
  72. #define SCLK_PMU 71
  73. #define SCLK_USBPHY_REF 72
  74. #define SCLK_WIFI 73
  75. #define SCLK_PVTM_PMU 74
  76. #define SCLK_PDM 75
  77. #define SCLK_I2S0_8CH_TX 76
  78. #define SCLK_I2S0_8CH_TX_OUT 77
  79. #define SCLK_I2S0_8CH_RX 78
  80. #define SCLK_I2S0_8CH_RX_OUT 79
  81. #define SCLK_I2S1_8CH_TX 80
  82. #define SCLK_I2S1_8CH_TX_OUT 81
  83. #define SCLK_I2S1_8CH_RX 82
  84. #define SCLK_I2S1_8CH_RX_OUT 83
  85. #define SCLK_I2S2_8CH_TX 84
  86. #define SCLK_I2S2_8CH_TX_OUT 85
  87. #define SCLK_I2S2_8CH_RX 86
  88. #define SCLK_I2S2_8CH_RX_OUT 87
  89. #define SCLK_I2S3_8CH_TX 88
  90. #define SCLK_I2S3_8CH_TX_OUT 89
  91. #define SCLK_I2S3_8CH_RX 90
  92. #define SCLK_I2S3_8CH_RX_OUT 91
  93. #define SCLK_I2S0_2CH 92
  94. #define SCLK_I2S0_2CH_OUT 93
  95. #define SCLK_I2S1_2CH 94
  96. #define SCLK_I2S1_2CH_OUT 95
  97. #define SCLK_SPDIF_TX_DIV 96
  98. #define SCLK_SPDIF_TX_DIV50 97
  99. #define SCLK_SPDIF_TX 98
  100. #define SCLK_SPDIF_RX_DIV 99
  101. #define SCLK_SPDIF_RX_DIV50 100
  102. #define SCLK_SPDIF_RX 101
  103. #define SCLK_I2S0_8CH_TX_MUX 102
  104. #define SCLK_I2S0_8CH_RX_MUX 103
  105. #define SCLK_I2S1_8CH_TX_MUX 104
  106. #define SCLK_I2S1_8CH_RX_MUX 105
  107. #define SCLK_I2S2_8CH_TX_MUX 106
  108. #define SCLK_I2S2_8CH_RX_MUX 107
  109. #define SCLK_I2S3_8CH_TX_MUX 108
  110. #define SCLK_I2S3_8CH_RX_MUX 109
  111. #define SCLK_I2S0_8CH_TX_SRC 110
  112. #define SCLK_I2S0_8CH_RX_SRC 111
  113. #define SCLK_I2S1_8CH_TX_SRC 112
  114. #define SCLK_I2S1_8CH_RX_SRC 113
  115. #define SCLK_I2S2_8CH_TX_SRC 114
  116. #define SCLK_I2S2_8CH_RX_SRC 115
  117. #define SCLK_I2S3_8CH_TX_SRC 116
  118. #define SCLK_I2S3_8CH_RX_SRC 117
  119. #define SCLK_I2S0_2CH_SRC 118
  120. #define SCLK_I2S1_2CH_SRC 119
  121. #define SCLK_PWM1 120
  122. #define SCLK_PWM2 121
  123. #define SCLK_OWIRE 122
  124. /* dclk */
  125. #define DCLK_VOP 125
  126. /* aclk */
  127. #define ACLK_BUS_SRC 130
  128. #define ACLK_BUS 131
  129. #define ACLK_PERI_SRC 132
  130. #define ACLK_PERI 133
  131. #define ACLK_MAC 134
  132. #define ACLK_CRYPTO 135
  133. #define ACLK_VOP 136
  134. #define ACLK_GIC 137
  135. #define ACLK_DMAC0 138
  136. #define ACLK_DMAC1 139
  137. /* hclk */
  138. #define HCLK_BUS 150
  139. #define HCLK_PERI 151
  140. #define HCLK_AUDIO 152
  141. #define HCLK_NANDC 153
  142. #define HCLK_SDMMC 154
  143. #define HCLK_SDIO 155
  144. #define HCLK_EMMC 156
  145. #define HCLK_SFC 157
  146. #define HCLK_OTG 158
  147. #define HCLK_HOST 159
  148. #define HCLK_HOST_ARB 160
  149. #define HCLK_PDM 161
  150. #define HCLK_SPDIFTX 162
  151. #define HCLK_SPDIFRX 163
  152. #define HCLK_I2S0_8CH 164
  153. #define HCLK_I2S1_8CH 165
  154. #define HCLK_I2S2_8CH 166
  155. #define HCLK_I2S3_8CH 167
  156. #define HCLK_I2S0_2CH 168
  157. #define HCLK_I2S1_2CH 169
  158. #define HCLK_VAD 170
  159. #define HCLK_CRYPTO 171
  160. #define HCLK_VOP 172
  161. /* pclk */
  162. #define PCLK_BUS 190
  163. #define PCLK_DDR 191
  164. #define PCLK_PERI 192
  165. #define PCLK_PMU 193
  166. #define PCLK_AUDIO 194
  167. #define PCLK_MAC 195
  168. #define PCLK_ACODEC 196
  169. #define PCLK_UART0 197
  170. #define PCLK_UART1 198
  171. #define PCLK_UART2 199
  172. #define PCLK_UART3 200
  173. #define PCLK_UART4 201
  174. #define PCLK_I2C0 202
  175. #define PCLK_I2C1 203
  176. #define PCLK_I2C2 204
  177. #define PCLK_I2C3 205
  178. #define PCLK_PWM0 206
  179. #define PCLK_SPI0 207
  180. #define PCLK_SPI1 208
  181. #define PCLK_SPI2 209
  182. #define PCLK_SARADC 210
  183. #define PCLK_TSADC 211
  184. #define PCLK_TIMER 212
  185. #define PCLK_OTP_NS 213
  186. #define PCLK_WDT 214
  187. #define PCLK_GPIO0 215
  188. #define PCLK_GPIO1 216
  189. #define PCLK_GPIO2 217
  190. #define PCLK_GPIO3 218
  191. #define PCLK_GPIO4 219
  192. #define PCLK_SGRF 220
  193. #define PCLK_GRF 221
  194. #define PCLK_USBSD_DET 222
  195. #define PCLK_DDR_UPCTL 223
  196. #define PCLK_DDR_MON 224
  197. #define PCLK_DDRPHY 225
  198. #define PCLK_DDR_STDBY 226
  199. #define PCLK_USB_GRF 227
  200. #define PCLK_CRU 228
  201. #define PCLK_OTP_PHY 229
  202. #define PCLK_CPU_BOOST 230
  203. #define PCLK_PWM1 231
  204. #define PCLK_PWM2 232
  205. #define PCLK_CAN 233
  206. #define PCLK_OWIRE 234
  207. #define CLK_NR_CLKS (PCLK_OWIRE + 1)
  208. /* soft-reset indices */
  209. /* cru_softrst_con0 */
  210. #define SRST_CORE0_PO 0
  211. #define SRST_CORE1_PO 1
  212. #define SRST_CORE2_PO 2
  213. #define SRST_CORE3_PO 3
  214. #define SRST_CORE0 4
  215. #define SRST_CORE1 5
  216. #define SRST_CORE2 6
  217. #define SRST_CORE3 7
  218. #define SRST_CORE0_DBG 8
  219. #define SRST_CORE1_DBG 9
  220. #define SRST_CORE2_DBG 10
  221. #define SRST_CORE3_DBG 11
  222. #define SRST_TOPDBG 12
  223. #define SRST_CORE_NOC 13
  224. #define SRST_STRC_A 14
  225. #define SRST_L2C 15
  226. /* cru_softrst_con1 */
  227. #define SRST_DAP 16
  228. #define SRST_CORE_PVTM 17
  229. #define SRST_CORE_PRF 18
  230. #define SRST_CORE_GRF 19
  231. #define SRST_DDRUPCTL 20
  232. #define SRST_DDRUPCTL_P 22
  233. #define SRST_MSCH 23
  234. #define SRST_DDRMON_P 25
  235. #define SRST_DDRSTDBY_P 26
  236. #define SRST_DDRSTDBY 27
  237. #define SRST_DDRPHY 28
  238. #define SRST_DDRPHY_DIV 29
  239. #define SRST_DDRPHY_P 30
  240. /* cru_softrst_con2 */
  241. #define SRST_BUS_NIU_H 32
  242. #define SRST_USB_NIU_P 33
  243. #define SRST_CRYPTO_A 34
  244. #define SRST_CRYPTO_H 35
  245. #define SRST_CRYPTO 36
  246. #define SRST_CRYPTO_APK 37
  247. #define SRST_VOP_A 38
  248. #define SRST_VOP_H 39
  249. #define SRST_VOP_D 40
  250. #define SRST_INTMEM_A 41
  251. #define SRST_ROM_H 42
  252. #define SRST_GIC_A 43
  253. #define SRST_UART0_P 44
  254. #define SRST_UART0 45
  255. #define SRST_UART1_P 46
  256. #define SRST_UART1 47
  257. /* cru_softrst_con3 */
  258. #define SRST_UART2_P 48
  259. #define SRST_UART2 49
  260. #define SRST_UART3_P 50
  261. #define SRST_UART3 51
  262. #define SRST_UART4_P 52
  263. #define SRST_UART4 53
  264. #define SRST_I2C0_P 54
  265. #define SRST_I2C0 55
  266. #define SRST_I2C1_P 56
  267. #define SRST_I2C1 57
  268. #define SRST_I2C2_P 58
  269. #define SRST_I2C2 59
  270. #define SRST_I2C3_P 60
  271. #define SRST_I2C3 61
  272. #define SRST_PWM0_P 62
  273. #define SRST_PWM0 63
  274. /* cru_softrst_con4 */
  275. #define SRST_SPI0_P 64
  276. #define SRST_SPI0 65
  277. #define SRST_SPI1_P 66
  278. #define SRST_SPI1 67
  279. #define SRST_SPI2_P 68
  280. #define SRST_SPI2 69
  281. #define SRST_SARADC_P 70
  282. #define SRST_TSADC_P 71
  283. #define SRST_TSADC 72
  284. #define SRST_TIMER0_P 73
  285. #define SRST_TIMER0 74
  286. #define SRST_TIMER1 75
  287. #define SRST_TIMER2 76
  288. #define SRST_TIMER3 77
  289. #define SRST_TIMER4 78
  290. #define SRST_TIMER5 79
  291. /* cru_softrst_con5 */
  292. #define SRST_OTP_NS_P 80
  293. #define SRST_OTP_NS_SBPI 81
  294. #define SRST_OTP_NS_USR 82
  295. #define SRST_OTP_PHY_P 83
  296. #define SRST_OTP_PHY 84
  297. #define SRST_GPIO0_P 86
  298. #define SRST_GPIO1_P 87
  299. #define SRST_GPIO2_P 88
  300. #define SRST_GPIO3_P 89
  301. #define SRST_GPIO4_P 90
  302. #define SRST_GRF_P 91
  303. #define SRST_USBSD_DET_P 92
  304. #define SRST_PMU 93
  305. #define SRST_PMU_PVTM 94
  306. #define SRST_USB_GRF_P 95
  307. /* cru_softrst_con6 */
  308. #define SRST_CPU_BOOST 96
  309. #define SRST_CPU_BOOST_P 97
  310. #define SRST_PWM1_P 98
  311. #define SRST_PWM1 99
  312. #define SRST_PWM2_P 100
  313. #define SRST_PWM2 101
  314. #define SRST_PERI_NIU_A 104
  315. #define SRST_PERI_NIU_H 105
  316. #define SRST_PERI_NIU_p 106
  317. #define SRST_USB2OTG_H 107
  318. #define SRST_USB2OTG 108
  319. #define SRST_USB2OTG_ADP 109
  320. #define SRST_USB2HOST_H 110
  321. #define SRST_USB2HOST_ARB_H 111
  322. /* cru_softrst_con7 */
  323. #define SRST_USB2HOST_AUX_H 112
  324. #define SRST_USB2HOST_EHCI 113
  325. #define SRST_USB2HOST 114
  326. #define SRST_USBPHYPOR 115
  327. #define SRST_UTMI0 116
  328. #define SRST_UTMI1 117
  329. #define SRST_SDIO_H 118
  330. #define SRST_EMMC_H 119
  331. #define SRST_SFC_H 120
  332. #define SRST_SFC 121
  333. #define SRST_SD_H 122
  334. #define SRST_NANDC_H 123
  335. #define SRST_NANDC_N 124
  336. #define SRST_MAC_A 125
  337. #define SRST_CAN_P 126
  338. #define SRST_OWIRE_P 127
  339. /* cru_softrst_con8 */
  340. #define SRST_AUDIO_NIU_H 128
  341. #define SRST_AUDIO_NIU_P 129
  342. #define SRST_PDM_H 130
  343. #define SRST_PDM_M 131
  344. #define SRST_SPDIFTX_H 132
  345. #define SRST_SPDIFTX_M 133
  346. #define SRST_SPDIFRX_H 134
  347. #define SRST_SPDIFRX_M 135
  348. #define SRST_I2S0_8CH_H 136
  349. #define SRST_I2S0_8CH_TX_M 137
  350. #define SRST_I2S0_8CH_RX_M 138
  351. #define SRST_I2S1_8CH_H 139
  352. #define SRST_I2S1_8CH_TX_M 140
  353. #define SRST_I2S1_8CH_RX_M 141
  354. #define SRST_I2S2_8CH_H 142
  355. #define SRST_I2S2_8CH_TX_M 143
  356. /* cru_softrst_con9 */
  357. #define SRST_I2S2_8CH_RX_M 144
  358. #define SRST_I2S3_8CH_H 145
  359. #define SRST_I2S3_8CH_TX_M 146
  360. #define SRST_I2S3_8CH_RX_M 147
  361. #define SRST_I2S0_2CH_H 148
  362. #define SRST_I2S0_2CH_M 149
  363. #define SRST_I2S1_2CH_H 150
  364. #define SRST_I2S1_2CH_M 151
  365. #define SRST_VAD_H 152
  366. #define SRST_ACODEC_P 153
  367. #endif