rk3228-cru.h 5.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
  4. */
  5. #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
  6. #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
  7. /* core clocks */
  8. #define PLL_APLL 1
  9. #define PLL_DPLL 2
  10. #define PLL_CPLL 3
  11. #define PLL_GPLL 4
  12. #define ARMCLK 5
  13. /* sclk gates (special clocks) */
  14. #define SCLK_SPI0 65
  15. #define SCLK_NANDC 67
  16. #define SCLK_SDMMC 68
  17. #define SCLK_SDIO 69
  18. #define SCLK_EMMC 71
  19. #define SCLK_TSADC 72
  20. #define SCLK_UART0 77
  21. #define SCLK_UART1 78
  22. #define SCLK_UART2 79
  23. #define SCLK_I2S0 80
  24. #define SCLK_I2S1 81
  25. #define SCLK_I2S2 82
  26. #define SCLK_SPDIF 83
  27. #define SCLK_TIMER0 85
  28. #define SCLK_TIMER1 86
  29. #define SCLK_TIMER2 87
  30. #define SCLK_TIMER3 88
  31. #define SCLK_TIMER4 89
  32. #define SCLK_TIMER5 90
  33. #define SCLK_I2S_OUT 113
  34. #define SCLK_SDMMC_DRV 114
  35. #define SCLK_SDIO_DRV 115
  36. #define SCLK_EMMC_DRV 117
  37. #define SCLK_SDMMC_SAMPLE 118
  38. #define SCLK_SDIO_SAMPLE 119
  39. #define SCLK_EMMC_SAMPLE 121
  40. #define SCLK_VOP 122
  41. #define SCLK_HDMI_HDCP 123
  42. #define SCLK_MAC_SRC 124
  43. #define SCLK_MAC_EXTCLK 125
  44. #define SCLK_MAC 126
  45. #define SCLK_MAC_REFOUT 127
  46. #define SCLK_MAC_REF 128
  47. #define SCLK_MAC_RX 129
  48. #define SCLK_MAC_TX 130
  49. #define SCLK_MAC_PHY 131
  50. #define SCLK_MAC_OUT 132
  51. /* dclk gates */
  52. #define DCLK_VOP 190
  53. #define DCLK_HDMI_PHY 191
  54. /* aclk gates */
  55. #define ACLK_DMAC 194
  56. #define ACLK_PERI 210
  57. #define ACLK_VOP 211
  58. #define ACLK_GMAC 212
  59. /* pclk gates */
  60. #define PCLK_GPIO0 320
  61. #define PCLK_GPIO1 321
  62. #define PCLK_GPIO2 322
  63. #define PCLK_GPIO3 323
  64. #define PCLK_GRF 329
  65. #define PCLK_I2C0 332
  66. #define PCLK_I2C1 333
  67. #define PCLK_I2C2 334
  68. #define PCLK_I2C3 335
  69. #define PCLK_SPI0 338
  70. #define PCLK_UART0 341
  71. #define PCLK_UART1 342
  72. #define PCLK_UART2 343
  73. #define PCLK_TSADC 344
  74. #define PCLK_PWM 350
  75. #define PCLK_TIMER 353
  76. #define PCLK_PERI 363
  77. #define PCLK_HDMI_CTRL 364
  78. #define PCLK_HDMI_PHY 365
  79. #define PCLK_GMAC 367
  80. /* hclk gates */
  81. #define HCLK_I2S0_8CH 442
  82. #define HCLK_I2S1_8CH 443
  83. #define HCLK_I2S2_2CH 444
  84. #define HCLK_SPDIF_8CH 445
  85. #define HCLK_VOP 452
  86. #define HCLK_NANDC 453
  87. #define HCLK_SDMMC 456
  88. #define HCLK_SDIO 457
  89. #define HCLK_EMMC 459
  90. #define HCLK_PERI 478
  91. #define CLK_NR_CLKS (HCLK_PERI + 1)
  92. /* soft-reset indices */
  93. #define SRST_CORE0_PO 0
  94. #define SRST_CORE1_PO 1
  95. #define SRST_CORE2_PO 2
  96. #define SRST_CORE3_PO 3
  97. #define SRST_CORE0 4
  98. #define SRST_CORE1 5
  99. #define SRST_CORE2 6
  100. #define SRST_CORE3 7
  101. #define SRST_CORE0_DBG 8
  102. #define SRST_CORE1_DBG 9
  103. #define SRST_CORE2_DBG 10
  104. #define SRST_CORE3_DBG 11
  105. #define SRST_TOPDBG 12
  106. #define SRST_ACLK_CORE 13
  107. #define SRST_NOC 14
  108. #define SRST_L2C 15
  109. #define SRST_CPUSYS_H 18
  110. #define SRST_BUSSYS_H 19
  111. #define SRST_SPDIF 20
  112. #define SRST_INTMEM 21
  113. #define SRST_ROM 22
  114. #define SRST_OTG_ADP 23
  115. #define SRST_I2S0 24
  116. #define SRST_I2S1 25
  117. #define SRST_I2S2 26
  118. #define SRST_ACODEC_P 27
  119. #define SRST_DFIMON 28
  120. #define SRST_MSCH 29
  121. #define SRST_EFUSE1024 30
  122. #define SRST_EFUSE256 31
  123. #define SRST_GPIO0 32
  124. #define SRST_GPIO1 33
  125. #define SRST_GPIO2 34
  126. #define SRST_GPIO3 35
  127. #define SRST_PERIPH_NOC_A 36
  128. #define SRST_PERIPH_NOC_BUS_H 37
  129. #define SRST_PERIPH_NOC_P 38
  130. #define SRST_UART0 39
  131. #define SRST_UART1 40
  132. #define SRST_UART2 41
  133. #define SRST_PHYNOC 42
  134. #define SRST_I2C0 43
  135. #define SRST_I2C1 44
  136. #define SRST_I2C2 45
  137. #define SRST_I2C3 46
  138. #define SRST_PWM 48
  139. #define SRST_A53_GIC 49
  140. #define SRST_DAP 51
  141. #define SRST_DAP_NOC 52
  142. #define SRST_CRYPTO 53
  143. #define SRST_SGRF 54
  144. #define SRST_GRF 55
  145. #define SRST_GMAC 56
  146. #define SRST_PERIPH_NOC_H 58
  147. #define SRST_MACPHY 63
  148. #define SRST_DMA 64
  149. #define SRST_NANDC 68
  150. #define SRST_USBOTG 69
  151. #define SRST_OTGC 70
  152. #define SRST_USBHOST0 71
  153. #define SRST_HOST_CTRL0 72
  154. #define SRST_USBHOST1 73
  155. #define SRST_HOST_CTRL1 74
  156. #define SRST_USBHOST2 75
  157. #define SRST_HOST_CTRL2 76
  158. #define SRST_USBPOR0 77
  159. #define SRST_USBPOR1 78
  160. #define SRST_DDRMSCH 79
  161. #define SRST_SMART_CARD 80
  162. #define SRST_SDMMC 81
  163. #define SRST_SDIO 82
  164. #define SRST_EMMC 83
  165. #define SRST_SPI 84
  166. #define SRST_TSP_H 85
  167. #define SRST_TSP 86
  168. #define SRST_TSADC 87
  169. #define SRST_DDRPHY 88
  170. #define SRST_DDRPHY_P 89
  171. #define SRST_DDRCTRL 90
  172. #define SRST_DDRCTRL_P 91
  173. #define SRST_HOST0_ECHI 92
  174. #define SRST_HOST1_ECHI 93
  175. #define SRST_HOST2_ECHI 94
  176. #define SRST_VOP_NOC_A 95
  177. #define SRST_HDMI_P 96
  178. #define SRST_VIO_ARBI_H 97
  179. #define SRST_IEP_NOC_A 98
  180. #define SRST_VIO_NOC_H 99
  181. #define SRST_VOP_A 100
  182. #define SRST_VOP_H 101
  183. #define SRST_VOP_D 102
  184. #define SRST_UTMI0 103
  185. #define SRST_UTMI1 104
  186. #define SRST_UTMI2 105
  187. #define SRST_UTMI3 106
  188. #define SRST_RGA 107
  189. #define SRST_RGA_NOC_A 108
  190. #define SRST_RGA_A 109
  191. #define SRST_RGA_H 110
  192. #define SRST_HDCP_A 111
  193. #define SRST_VPU_A 112
  194. #define SRST_VPU_H 113
  195. #define SRST_VPU_NOC_A 116
  196. #define SRST_VPU_NOC_H 117
  197. #define SRST_RKVDEC_A 118
  198. #define SRST_RKVDEC_NOC_A 119
  199. #define SRST_RKVDEC_H 120
  200. #define SRST_RKVDEC_NOC_H 121
  201. #define SRST_RKVDEC_CORE 122
  202. #define SRST_RKVDEC_CABAC 123
  203. #define SRST_IEP_A 124
  204. #define SRST_IEP_H 125
  205. #define SRST_GPU_A 126
  206. #define SRST_GPU_NOC_A 127
  207. #define SRST_CORE_DBG 128
  208. #define SRST_DBG_P 129
  209. #define SRST_TIMER0 130
  210. #define SRST_TIMER1 131
  211. #define SRST_TIMER2 132
  212. #define SRST_TIMER3 133
  213. #define SRST_TIMER4 134
  214. #define SRST_TIMER5 135
  215. #define SRST_VIO_H2P 136
  216. #define SRST_HDMIPHY 139
  217. #define SRST_VDAC 140
  218. #define SRST_TIMER_6CH_P 141
  219. #endif