omap5.h 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright 2017 Texas Instruments, Inc.
  4. */
  5. #ifndef __DT_BINDINGS_CLK_OMAP5_H
  6. #define __DT_BINDINGS_CLK_OMAP5_H
  7. #define OMAP5_CLKCTRL_OFFSET 0x20
  8. #define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET)
  9. /* mpu clocks */
  10. #define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  11. /* dsp clocks */
  12. #define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  13. /* abe clocks */
  14. #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  15. #define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
  16. #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
  17. #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
  18. #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
  19. #define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
  20. #define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
  21. #define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
  22. #define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
  23. #define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
  24. #define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
  25. /* l3main1 clocks */
  26. #define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  27. /* l3main2 clocks */
  28. #define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  29. /* ipu clocks */
  30. #define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  31. /* dma clocks */
  32. #define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  33. /* emif clocks */
  34. #define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  35. #define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
  36. #define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
  37. /* l4cfg clocks */
  38. #define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  39. #define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
  40. #define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
  41. /* l3instr clocks */
  42. #define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  43. #define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
  44. /* l4per clocks */
  45. #define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
  46. #define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
  47. #define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
  48. #define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
  49. #define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
  50. #define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
  51. #define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60)
  52. #define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
  53. #define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
  54. #define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
  55. #define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
  56. #define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0)
  57. #define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8)
  58. #define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0)
  59. #define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8)
  60. #define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0)
  61. #define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
  62. #define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8)
  63. #define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100)
  64. #define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108)
  65. #define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110)
  66. #define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118)
  67. #define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120)
  68. #define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128)
  69. #define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140)
  70. #define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148)
  71. #define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150)
  72. #define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158)
  73. #define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160)
  74. #define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168)
  75. #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
  76. #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
  77. /* l4_secure clocks */
  78. #define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0
  79. #define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET)
  80. #define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0)
  81. #define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8)
  82. #define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0)
  83. #define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8)
  84. #define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0)
  85. #define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8)
  86. #define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8)
  87. /* iva clocks */
  88. #define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  89. #define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
  90. /* dss clocks */
  91. #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  92. /* gpu clocks */
  93. #define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  94. /* l3init clocks */
  95. #define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
  96. #define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
  97. #define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
  98. #define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
  99. #define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88)
  100. #define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0)
  101. #define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8)
  102. #define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
  103. /* wkupaon clocks */
  104. #define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
  105. #define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
  106. #define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
  107. #define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
  108. #define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
  109. #define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
  110. #endif