mt8518-clk.h 7.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2019 MediaTek Inc.
  4. */
  5. #ifndef _DT_BINDINGS_CLK_MT8518_H
  6. #define _DT_BINDINGS_CLK_MT8518_H
  7. /* APMIXEDSYS */
  8. #define CLK_APMIXED_ARMPLL 0
  9. #define CLK_APMIXED_MAINPLL 1
  10. #define CLK_APMIXED_UNIVPLL 2
  11. #define CLK_APMIXED_MMPLL 3
  12. #define CLK_APMIXED_APLL1 4
  13. #define CLK_APMIXED_APLL2 5
  14. #define CLK_APMIXED_TVDPLL 6
  15. #define CLK_APMIXED_NR_CLK 7
  16. /* TOPCKGEN */
  17. #define CLK_TOP_CLK_NULL 0
  18. #define CLK_TOP_FQ_TRNG_OUT0 1
  19. #define CLK_TOP_FQ_TRNG_OUT1 2
  20. #define CLK_TOP_CLK32K 3
  21. #define CLK_TOP_DMPLL 4
  22. #define CLK_TOP_MAINPLL_D4 5
  23. #define CLK_TOP_MAINPLL_D8 6
  24. #define CLK_TOP_MAINPLL_D16 7
  25. #define CLK_TOP_MAINPLL_D11 8
  26. #define CLK_TOP_MAINPLL_D22 9
  27. #define CLK_TOP_MAINPLL_D3 10
  28. #define CLK_TOP_MAINPLL_D6 11
  29. #define CLK_TOP_MAINPLL_D12 12
  30. #define CLK_TOP_MAINPLL_D5 13
  31. #define CLK_TOP_MAINPLL_D10 14
  32. #define CLK_TOP_MAINPLL_D20 15
  33. #define CLK_TOP_MAINPLL_D40 16
  34. #define CLK_TOP_MAINPLL_D7 17
  35. #define CLK_TOP_MAINPLL_D14 18
  36. #define CLK_TOP_UNIVPLL_D2 19
  37. #define CLK_TOP_UNIVPLL_D4 20
  38. #define CLK_TOP_UNIVPLL_D8 21
  39. #define CLK_TOP_UNIVPLL_D16 22
  40. #define CLK_TOP_UNIVPLL_D3 23
  41. #define CLK_TOP_UNIVPLL_D6 24
  42. #define CLK_TOP_UNIVPLL_D12 25
  43. #define CLK_TOP_UNIVPLL_D24 26
  44. #define CLK_TOP_UNIVPLL_D5 27
  45. #define CLK_TOP_UNIVPLL_D20 28
  46. #define CLK_TOP_UNIVPLL_D10 29
  47. #define CLK_TOP_MMPLL_D2 30
  48. #define CLK_TOP_USB20_48M 31
  49. #define CLK_TOP_APLL1 32
  50. #define CLK_TOP_APLL1_D4 33
  51. #define CLK_TOP_APLL2 34
  52. #define CLK_TOP_APLL2_D2 35
  53. #define CLK_TOP_APLL2_D3 36
  54. #define CLK_TOP_APLL2_D4 37
  55. #define CLK_TOP_APLL2_D8 38
  56. #define CLK_TOP_CLK26M 39
  57. #define CLK_TOP_CLK26M_D2 40
  58. #define CLK_TOP_CLK26M_D4 41
  59. #define CLK_TOP_CLK26M_D8 42
  60. #define CLK_TOP_CLK26M_D793 43
  61. #define CLK_TOP_TVDPLL 44
  62. #define CLK_TOP_TVDPLL_D2 45
  63. #define CLK_TOP_TVDPLL_D4 46
  64. #define CLK_TOP_TVDPLL_D8 47
  65. #define CLK_TOP_TVDPLL_D16 48
  66. #define CLK_TOP_USB20_CLK480M 49
  67. #define CLK_TOP_RG_APLL1_D2 50
  68. #define CLK_TOP_RG_APLL1_D4 51
  69. #define CLK_TOP_RG_APLL1_D8 52
  70. #define CLK_TOP_RG_APLL1_D16 53
  71. #define CLK_TOP_RG_APLL1_D3 54
  72. #define CLK_TOP_RG_APLL2_D2 55
  73. #define CLK_TOP_RG_APLL2_D4 56
  74. #define CLK_TOP_RG_APLL2_D8 57
  75. #define CLK_TOP_RG_APLL2_D16 58
  76. #define CLK_TOP_RG_APLL2_D3 59
  77. #define CLK_TOP_NFI1X_INFRA_BCLK 60
  78. #define CLK_TOP_AHB_INFRA_D2 61
  79. #define CLK_TOP_UART0_SEL 62
  80. #define CLK_TOP_EMI1X_SEL 63
  81. #define CLK_TOP_EMI_DDRPHY_SEL 64
  82. #define CLK_TOP_MSDC1_SEL 65
  83. #define CLK_TOP_PWM_MM_SEL 66
  84. #define CLK_TOP_UART1_SEL 67
  85. #define CLK_TOP_SPM_52M_SEL 68
  86. #define CLK_TOP_PMICSPI_SEL 69
  87. #define CLK_TOP_NFI2X_SEL 70
  88. #define CLK_TOP_DDRPHYCFG_SEL 71
  89. #define CLK_TOP_SMI_SEL 72
  90. #define CLK_TOP_USB_SEL 73
  91. #define CLK_TOP_SPINOR_SEL 74
  92. #define CLK_TOP_ETH_SEL 75
  93. #define CLK_TOP_AUD1_SEL 76
  94. #define CLK_TOP_AUD2_SEL 77
  95. #define CLK_TOP_I2C_SEL 78
  96. #define CLK_TOP_AUD_I2S0_M_SEL 79
  97. #define CLK_TOP_AUD_I2S3_M_SEL 80
  98. #define CLK_TOP_AUD_I2S4_M_SEL 81
  99. #define CLK_TOP_AUD_I2S6_M_SEL 82
  100. #define CLK_TOP_PWM_SEL 83
  101. #define CLK_TOP_AUD_SPDIFIN_SEL 84
  102. #define CLK_TOP_UART2_SEL 85
  103. #define CLK_TOP_DBG_ATCLK_SEL 86
  104. #define CLK_TOP_PNG_SYS_SEL 87
  105. #define CLK_TOP_SEJ_13M_SEL 88
  106. #define CLK_TOP_IMGRZ_SYS_SEL 89
  107. #define CLK_TOP_GRAPH_ECLK_SEL 90
  108. #define CLK_TOP_FDBI_SEL 91
  109. #define CLK_TOP_FAUDIO_SEL 92
  110. #define CLK_TOP_FA2SYS_SEL 93
  111. #define CLK_TOP_FA1SYS_SEL 94
  112. #define CLK_TOP_FASM_M_SEL 95
  113. #define CLK_TOP_FASM_H_SEL 96
  114. #define CLK_TOP_FASM_L_SEL 97
  115. #define CLK_TOP_FECC_CK_SEL 98
  116. #define CLK_TOP_PE2_MAC_SEL 99
  117. #define CLK_TOP_CMSYS_SEL 100
  118. #define CLK_TOP_GCPU_SEL 101
  119. #define CLK_TOP_SPIS_CK_SEL 102
  120. #define CLK_TOP_APLL1_REF_SEL 103
  121. #define CLK_TOP_APLL2_REF_SEL 104
  122. #define CLK_TOP_INT_32K_SEL 105
  123. #define CLK_TOP_APLL1_SRC_SEL 106
  124. #define CLK_TOP_APLL2_SRC_SEL 107
  125. #define CLK_TOP_FAUD_INTBUS_SEL 108
  126. #define CLK_TOP_AXIBUS_SEL 109
  127. #define CLK_TOP_HAPLL1_SEL 110
  128. #define CLK_TOP_HAPLL2_SEL 111
  129. #define CLK_TOP_SPINFI_SEL 112
  130. #define CLK_TOP_MSDC0_SEL 113
  131. #define CLK_TOP_MSDC0_CLK50_SEL 114
  132. #define CLK_TOP_MSDC2_SEL 115
  133. #define CLK_TOP_MSDC2_CLK50_SEL 116
  134. #define CLK_TOP_DISP_DPI_CK_SEL 117
  135. #define CLK_TOP_SPI1_SEL 118
  136. #define CLK_TOP_SPI2_SEL 119
  137. #define CLK_TOP_SPI3_SEL 120
  138. #define CLK_TOP_APLL12_CK_DIV0 121
  139. #define CLK_TOP_APLL12_CK_DIV3 122
  140. #define CLK_TOP_APLL12_CK_DIV4 123
  141. #define CLK_TOP_APLL12_CK_DIV6 124
  142. /* TOPCKGEN Gates */
  143. #define CLK_TOP_PWM_MM 0
  144. #define CLK_TOP_SMI 1
  145. #define CLK_TOP_SPI2 2
  146. #define CLK_TOP_SPI3 3
  147. #define CLK_TOP_SPINFI 4
  148. #define CLK_TOP_26M_DEBUG 5
  149. #define CLK_TOP_USB_48M_DEBUG 6
  150. #define CLK_TOP_52M_DEBUG 7
  151. #define CLK_TOP_32K_DEBUG 8
  152. #define CLK_TOP_THERM 9
  153. #define CLK_TOP_APDMA 10
  154. #define CLK_TOP_I2C0 11
  155. #define CLK_TOP_I2C1 12
  156. #define CLK_TOP_AUXADC1 13
  157. #define CLK_TOP_NFI 14
  158. #define CLK_TOP_NFIECC 15
  159. #define CLK_TOP_DEBUGSYS 16
  160. #define CLK_TOP_PWM 17
  161. #define CLK_TOP_UART0 18
  162. #define CLK_TOP_UART1 19
  163. #define CLK_TOP_USB 20
  164. #define CLK_TOP_FLASHIF_26M 21
  165. #define CLK_TOP_AUXADC2 22
  166. #define CLK_TOP_I2C2 23
  167. #define CLK_TOP_MSDC0 24
  168. #define CLK_TOP_MSDC1 25
  169. #define CLK_TOP_NFI2X 26
  170. #define CLK_TOP_MEMSLP_DLYER 27
  171. #define CLK_TOP_SPI 28
  172. #define CLK_TOP_APXGPT 29
  173. #define CLK_TOP_PMICWRAP_MD 30
  174. #define CLK_TOP_PMICWRAP_CONN 31
  175. #define CLK_TOP_PMIC_SYSCK 32
  176. #define CLK_TOP_AUX_ADC 33
  177. #define CLK_TOP_AUX_TP 34
  178. #define CLK_TOP_RBIST 35
  179. #define CLK_TOP_NFI_BUS 36
  180. #define CLK_TOP_GCE 37
  181. #define CLK_TOP_TRNG 38
  182. #define CLK_TOP_PWM_B 39
  183. #define CLK_TOP_PWM1_FB 40
  184. #define CLK_TOP_PWM2_FB 41
  185. #define CLK_TOP_PWM3_FB 42
  186. #define CLK_TOP_PWM4_FB 43
  187. #define CLK_TOP_PWM5_FB 44
  188. #define CLK_TOP_FLASHIF_FREERUN 45
  189. #define CLK_TOP_CQDMA 46
  190. #define CLK_TOP_66M_ETH 47
  191. #define CLK_TOP_133M_ETH 48
  192. #define CLK_TOP_FLASHIF_AXI 49
  193. #define CLK_TOP_USBIF 50
  194. #define CLK_TOP_UART2 51
  195. #define CLK_TOP_GCPU_B 52
  196. #define CLK_TOP_MSDC0_B 53
  197. #define CLK_TOP_MSDC1_B 54
  198. #define CLK_TOP_MSDC2_B 55
  199. #define CLK_TOP_USB_B 56
  200. #define CLK_TOP_SPINOR 57
  201. #define CLK_TOP_MSDC2 58
  202. #define CLK_TOP_ETH 59
  203. #define CLK_TOP_AUD1 60
  204. #define CLK_TOP_AUD2 61
  205. #define CLK_TOP_I2C 62
  206. #define CLK_TOP_PWM_INFRA 63
  207. #define CLK_TOP_AUD_SPDIF_IN 64
  208. #define CLK_TOP_RG_UART2 65
  209. #define CLK_TOP_DBG_AT 66
  210. #define CLK_TOP_APLL12_DIV0 67
  211. #define CLK_TOP_APLL12_DIV3 68
  212. #define CLK_TOP_APLL12_DIV4 69
  213. #define CLK_TOP_APLL12_DIV6 70
  214. #define CLK_TOP_IMGRZ_SYS 71
  215. #define CLK_TOP_PNG_SYS 72
  216. #define CLK_TOP_GRAPH_E 73
  217. #define CLK_TOP_FDBI 74
  218. #define CLK_TOP_FAUDIO 75
  219. #define CLK_TOP_FAUD_INTBUS 76
  220. #define CLK_TOP_HAPLL1 77
  221. #define CLK_TOP_HAPLL2 78
  222. #define CLK_TOP_FA2SYS 79
  223. #define CLK_TOP_FA1SYS 80
  224. #define CLK_TOP_FASM_L 81
  225. #define CLK_TOP_FASM_M 82
  226. #define CLK_TOP_FASM_H 83
  227. #define CLK_TOP_FECC 84
  228. #define CLK_TOP_PE2_MAC 85
  229. #define CLK_TOP_CMSYS 86
  230. #define CLK_TOP_GCPU 87
  231. #define CLK_TOP_SPIS 88
  232. #define CLK_TOP_I2C3 89
  233. #define CLK_TOP_SPI_SLV_B 90
  234. #define CLK_TOP_SPI_SLV_BUS 91
  235. #define CLK_TOP_PCIE_MAC_BUS 92
  236. #define CLK_TOP_CMSYS_BUS 93
  237. #define CLK_TOP_ECC_B 94
  238. #define CLK_TOP_PCIE_PHY_BUS 95
  239. #define CLK_TOP_PCIE_AUX 96
  240. #define CLK_TOP_DISP_DPI 97
  241. #define CLK_TOP_NR_CLK 98
  242. #endif /* _DT_BINDINGS_CLK_MT8518_H */