mt8512-clk.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2019 MediaTek Inc.
  4. */
  5. #ifndef _DT_BINDINGS_CLK_MT8512_H
  6. #define _DT_BINDINGS_CLK_MT8512_H
  7. /* TOPCKGEN */
  8. #define CLK_TOP_CLK_NULL 0
  9. #define CLK_TOP_CLK32K 1
  10. #define CLK_TOP_SYSPLL1_D2 2
  11. #define CLK_TOP_SYSPLL1_D4 3
  12. #define CLK_TOP_SYSPLL1_D8 4
  13. #define CLK_TOP_SYSPLL1_D16 5
  14. #define CLK_TOP_SYSPLL_D3 6
  15. #define CLK_TOP_SYSPLL2_D2 7
  16. #define CLK_TOP_SYSPLL2_D4 8
  17. #define CLK_TOP_SYSPLL2_D8 9
  18. #define CLK_TOP_SYSPLL_D5 10
  19. #define CLK_TOP_SYSPLL3_D4 11
  20. #define CLK_TOP_SYSPLL_D7 12
  21. #define CLK_TOP_SYSPLL4_D2 13
  22. #define CLK_TOP_UNIVPLL 14
  23. #define CLK_TOP_UNIVPLL_D2 15
  24. #define CLK_TOP_UNIVPLL1_D2 16
  25. #define CLK_TOP_UNIVPLL1_D4 17
  26. #define CLK_TOP_UNIVPLL1_D8 18
  27. #define CLK_TOP_UNIVPLL_D3 19
  28. #define CLK_TOP_UNIVPLL2_D2 20
  29. #define CLK_TOP_UNIVPLL2_D4 21
  30. #define CLK_TOP_UNIVPLL2_D8 22
  31. #define CLK_TOP_UNIVPLL_D5 23
  32. #define CLK_TOP_UNIVPLL3_D2 24
  33. #define CLK_TOP_UNIVPLL3_D4 25
  34. #define CLK_TOP_TCONPLL_D2 26
  35. #define CLK_TOP_TCONPLL_D4 27
  36. #define CLK_TOP_TCONPLL_D8 28
  37. #define CLK_TOP_TCONPLL_D16 29
  38. #define CLK_TOP_TCONPLL_D32 30
  39. #define CLK_TOP_TCONPLL_D64 31
  40. #define CLK_TOP_USB20_192M 32
  41. #define CLK_TOP_USB20_192M_D2 33
  42. #define CLK_TOP_USB20_192M_D4_T 34
  43. #define CLK_TOP_APLL1 35
  44. #define CLK_TOP_APLL1_D2 36
  45. #define CLK_TOP_APLL1_D3 37
  46. #define CLK_TOP_APLL1_D4 38
  47. #define CLK_TOP_APLL1_D8 39
  48. #define CLK_TOP_APLL1_D16 40
  49. #define CLK_TOP_APLL2 41
  50. #define CLK_TOP_APLL2_D2 42
  51. #define CLK_TOP_APLL2_D3 43
  52. #define CLK_TOP_APLL2_D4 44
  53. #define CLK_TOP_APLL2_D8 45
  54. #define CLK_TOP_APLL2_D16 46
  55. #define CLK_TOP_CLK26M 47
  56. #define CLK_TOP_SYS_26M_D2 48
  57. #define CLK_TOP_MSDCPLL 49
  58. #define CLK_TOP_MSDCPLL_D2 50
  59. #define CLK_TOP_DSPPLL 51
  60. #define CLK_TOP_DSPPLL_D2 52
  61. #define CLK_TOP_DSPPLL_D4 53
  62. #define CLK_TOP_DSPPLL_D8 54
  63. #define CLK_TOP_IPPLL 55
  64. #define CLK_TOP_IPPLL_D2 56
  65. #define CLK_TOP_NFI2X_CK_D2 57
  66. #define CLK_TOP_AXI_SEL 58
  67. #define CLK_TOP_MEM_SEL 59
  68. #define CLK_TOP_UART_SEL 60
  69. #define CLK_TOP_SPI_SEL 61
  70. #define CLK_TOP_SPIS_SEL 62
  71. #define CLK_TOP_MSDC50_0_HC_SEL 63
  72. #define CLK_TOP_MSDC2_2_HC_SEL 64
  73. #define CLK_TOP_MSDC50_0_SEL 65
  74. #define CLK_TOP_MSDC50_2_SEL 66
  75. #define CLK_TOP_MSDC30_1_SEL 67
  76. #define CLK_TOP_AUDIO_SEL 68
  77. #define CLK_TOP_AUD_INTBUS_SEL 69
  78. #define CLK_TOP_HAPLL1_SEL 70
  79. #define CLK_TOP_HAPLL2_SEL 71
  80. #define CLK_TOP_A2SYS_SEL 72
  81. #define CLK_TOP_A1SYS_SEL 73
  82. #define CLK_TOP_ASM_L_SEL 74
  83. #define CLK_TOP_ASM_M_SEL 75
  84. #define CLK_TOP_ASM_H_SEL 76
  85. #define CLK_TOP_AUD_SPDIF_SEL 77
  86. #define CLK_TOP_AUD_1_SEL 78
  87. #define CLK_TOP_AUD_2_SEL 79
  88. #define CLK_TOP_SSUSB_SYS_SEL 80
  89. #define CLK_TOP_SSUSB_XHCI_SEL 81
  90. #define CLK_TOP_SPM_SEL 82
  91. #define CLK_TOP_I2C_SEL 83
  92. #define CLK_TOP_PWM_SEL 84
  93. #define CLK_TOP_DSP_SEL 85
  94. #define CLK_TOP_NFI2X_SEL 86
  95. #define CLK_TOP_SPINFI_SEL 87
  96. #define CLK_TOP_ECC_SEL 88
  97. #define CLK_TOP_GCPU_SEL 89
  98. #define CLK_TOP_GCPU_CPM_SEL 90
  99. #define CLK_TOP_MBIST_DIAG_SEL 91
  100. #define CLK_TOP_IP0_NNA_SEL 92
  101. #define CLK_TOP_IP1_NNA_SEL 93
  102. #define CLK_TOP_IP2_WFST_SEL 94
  103. #define CLK_TOP_SFLASH_SEL 95
  104. #define CLK_TOP_SRAM_SEL 96
  105. #define CLK_TOP_MM_SEL 97
  106. #define CLK_TOP_DPI0_SEL 98
  107. #define CLK_TOP_DBG_ATCLK_SEL 99
  108. #define CLK_TOP_OCC_104M_SEL 100
  109. #define CLK_TOP_OCC_68M_SEL 101
  110. #define CLK_TOP_OCC_182M_SEL 102
  111. /* TOPCKGEN Gates */
  112. #define CLK_TOP_CONN_32K 0
  113. #define CLK_TOP_CONN_26M 1
  114. #define CLK_TOP_DSP_32K 2
  115. #define CLK_TOP_DSP_26M 3
  116. #define CLK_TOP_USB20_48M_EN 4
  117. #define CLK_TOP_UNIVPLL_48M_EN 5
  118. #define CLK_TOP_SSUSB_TOP_CK_EN 6
  119. #define CLK_TOP_SSUSB_PHY_CK_EN 7
  120. #define CLK_TOP_I2SI1_MCK 8
  121. #define CLK_TOP_TDMIN_MCK 9
  122. #define CLK_TOP_I2SO1_MCK 10
  123. /* INFRASYS */
  124. #define CLK_INFRA_DSP_AXI 0
  125. #define CLK_INFRA_APXGPT 1
  126. #define CLK_INFRA_ICUSB 2
  127. #define CLK_INFRA_GCE 3
  128. #define CLK_INFRA_THERM 4
  129. #define CLK_INFRA_PWM_HCLK 5
  130. #define CLK_INFRA_PWM1 6
  131. #define CLK_INFRA_PWM2 7
  132. #define CLK_INFRA_PWM3 8
  133. #define CLK_INFRA_PWM4 9
  134. #define CLK_INFRA_PWM5 10
  135. #define CLK_INFRA_PWM 11
  136. #define CLK_INFRA_UART0 12
  137. #define CLK_INFRA_UART1 13
  138. #define CLK_INFRA_UART2 14
  139. #define CLK_INFRA_DSP_UART 15
  140. #define CLK_INFRA_GCE_26M 16
  141. #define CLK_INFRA_CQDMA_FPC 17
  142. #define CLK_INFRA_BTIF 18
  143. #define CLK_INFRA_SPI 19
  144. #define CLK_INFRA_MSDC0 20
  145. #define CLK_INFRA_MSDC1 21
  146. #define CLK_INFRA_DVFSRC 22
  147. #define CLK_INFRA_GCPU 23
  148. #define CLK_INFRA_TRNG 24
  149. #define CLK_INFRA_AUXADC 25
  150. #define CLK_INFRA_AUXADC_MD 26
  151. #define CLK_INFRA_AP_DMA 27
  152. #define CLK_INFRA_DEBUGSYS 28
  153. #define CLK_INFRA_AUDIO 29
  154. #define CLK_INFRA_FLASHIF 30
  155. #define CLK_INFRA_PWM_FB6 31
  156. #define CLK_INFRA_PWM_FB7 32
  157. #define CLK_INFRA_AUD_ASRC 33
  158. #define CLK_INFRA_AUD_26M 34
  159. #define CLK_INFRA_SPIS 35
  160. #define CLK_INFRA_CQ_DMA 36
  161. #define CLK_INFRA_AP_MSDC0 37
  162. #define CLK_INFRA_MD_MSDC0 38
  163. #define CLK_INFRA_MSDC0_SRC 39
  164. #define CLK_INFRA_MSDC1_SRC 40
  165. #define CLK_INFRA_IRRX_26M 41
  166. #define CLK_INFRA_IRRX_32K 42
  167. #define CLK_INFRA_I2C0_AXI 43
  168. #define CLK_INFRA_I2C1_AXI 44
  169. #define CLK_INFRA_I2C2_AXI 45
  170. #define CLK_INFRA_NFI 46
  171. #define CLK_INFRA_NFIECC 47
  172. #define CLK_INFRA_NFI_HCLK 48
  173. #define CLK_INFRA_SUSB_133 49
  174. #define CLK_INFRA_USB_SYS 50
  175. #define CLK_INFRA_USB_XHCI 51
  176. #define CLK_INFRA_NR_CLK 52
  177. /* APMIXEDSYS */
  178. #define CLK_APMIXED_ARMPLL 0
  179. #define CLK_APMIXED_MAINPLL 1
  180. #define CLK_APMIXED_UNIVPLL2 2
  181. #define CLK_APMIXED_MSDCPLL 3
  182. #define CLK_APMIXED_APLL1 4
  183. #define CLK_APMIXED_APLL2 5
  184. #define CLK_APMIXED_IPPLL 6
  185. #define CLK_APMIXED_DSPPLL 7
  186. #define CLK_APMIXED_TCONPLL 8
  187. #define CLK_APMIXED_NR_CLK 9
  188. #endif /* _DT_BINDINGS_CLK_MT8512_H */