mt7623-clk.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. */
  5. #ifndef _DT_BINDINGS_CLK_MT2701_H
  6. #define _DT_BINDINGS_CLK_MT2701_H
  7. /* TOPCKGEN */
  8. #define CLK_TOP_FCLKS_OFF 0
  9. #define CLK_TOP_DPI 0
  10. #define CLK_TOP_DMPLL 1
  11. #define CLK_TOP_VENCPLL 2
  12. #define CLK_TOP_HDMI_0_PIX340M 3
  13. #define CLK_TOP_HDMI_0_DEEP340M 4
  14. #define CLK_TOP_HDMI_0_PLL340M 5
  15. #define CLK_TOP_HADDS2_FB 6
  16. #define CLK_TOP_WBG_DIG_416M 7
  17. #define CLK_TOP_DSI0_LNTC_DSI 8
  18. #define CLK_TOP_HDMI_SCL_RX 9
  19. #define CLK_TOP_32K_EXTERNAL 10
  20. #define CLK_TOP_HDMITX_CLKDIG_CTS 11
  21. #define CLK_TOP_AUD_EXT1 12
  22. #define CLK_TOP_AUD_EXT2 13
  23. #define CLK_TOP_NFI1X_PAD 14
  24. #define CLK_TOP_SYSPLL 15
  25. #define CLK_TOP_SYSPLL_D2 16
  26. #define CLK_TOP_SYSPLL_D3 17
  27. #define CLK_TOP_SYSPLL_D5 18
  28. #define CLK_TOP_SYSPLL_D7 19
  29. #define CLK_TOP_SYSPLL1_D2 20
  30. #define CLK_TOP_SYSPLL1_D4 21
  31. #define CLK_TOP_SYSPLL1_D8 22
  32. #define CLK_TOP_SYSPLL1_D16 23
  33. #define CLK_TOP_SYSPLL2_D2 24
  34. #define CLK_TOP_SYSPLL2_D4 25
  35. #define CLK_TOP_SYSPLL2_D8 26
  36. #define CLK_TOP_SYSPLL3_D2 27
  37. #define CLK_TOP_SYSPLL3_D4 28
  38. #define CLK_TOP_SYSPLL4_D2 29
  39. #define CLK_TOP_SYSPLL4_D4 30
  40. #define CLK_TOP_UNIVPLL 31
  41. #define CLK_TOP_UNIVPLL_D2 32
  42. #define CLK_TOP_UNIVPLL_D3 33
  43. #define CLK_TOP_UNIVPLL_D5 34
  44. #define CLK_TOP_UNIVPLL_D7 35
  45. #define CLK_TOP_UNIVPLL_D26 36
  46. #define CLK_TOP_UNIVPLL_D52 37
  47. #define CLK_TOP_UNIVPLL_D108 38
  48. #define CLK_TOP_USB_PHY48M 39
  49. #define CLK_TOP_UNIVPLL1_D2 40
  50. #define CLK_TOP_UNIVPLL1_D4 41
  51. #define CLK_TOP_UNIVPLL1_D8 42
  52. #define CLK_TOP_UNIVPLL2_D2 43
  53. #define CLK_TOP_UNIVPLL2_D4 44
  54. #define CLK_TOP_UNIVPLL2_D8 45
  55. #define CLK_TOP_UNIVPLL2_D16 46
  56. #define CLK_TOP_UNIVPLL2_D32 47
  57. #define CLK_TOP_UNIVPLL3_D2 48
  58. #define CLK_TOP_UNIVPLL3_D4 49
  59. #define CLK_TOP_UNIVPLL3_D8 50
  60. #define CLK_TOP_MSDCPLL 51
  61. #define CLK_TOP_MSDCPLL_D2 52
  62. #define CLK_TOP_MSDCPLL_D4 53
  63. #define CLK_TOP_MSDCPLL_D8 54
  64. #define CLK_TOP_MMPLL 55
  65. #define CLK_TOP_MMPLL_D2 56
  66. #define CLK_TOP_DMPLL_D2 57
  67. #define CLK_TOP_DMPLL_D4 58
  68. #define CLK_TOP_DMPLL_X2 59
  69. #define CLK_TOP_TVDPLL 60
  70. #define CLK_TOP_TVDPLL_D2 61
  71. #define CLK_TOP_TVDPLL_D4 62
  72. #define CLK_TOP_VDECPLL 63
  73. #define CLK_TOP_TVD2PLL 64
  74. #define CLK_TOP_TVD2PLL_D2 65
  75. #define CLK_TOP_MIPIPLL 66
  76. #define CLK_TOP_MIPIPLL_D2 67
  77. #define CLK_TOP_MIPIPLL_D4 68
  78. #define CLK_TOP_HDMIPLL 69
  79. #define CLK_TOP_HDMIPLL_D2 70
  80. #define CLK_TOP_HDMIPLL_D3 71
  81. #define CLK_TOP_ARMPLL_1P3G 72
  82. #define CLK_TOP_AUDPLL 73
  83. #define CLK_TOP_AUDPLL_D4 74
  84. #define CLK_TOP_AUDPLL_D8 75
  85. #define CLK_TOP_AUDPLL_D16 76
  86. #define CLK_TOP_AUDPLL_D24 77
  87. #define CLK_TOP_AUD1PLL_98M 78
  88. #define CLK_TOP_AUD2PLL_90M 79
  89. #define CLK_TOP_HADDS2PLL_98M 80
  90. #define CLK_TOP_HADDS2PLL_294M 81
  91. #define CLK_TOP_ETHPLL_500M 82
  92. #define CLK_TOP_CLK26M_D8 83
  93. #define CLK_TOP_32K_INTERNAL 84
  94. #define CLK_TOP_AXISEL_D4 85
  95. #define CLK_TOP_8BDAC 86
  96. #define CLK_TOP_AXI_SEL 87
  97. #define CLK_TOP_MEM_SEL 88
  98. #define CLK_TOP_DDRPHYCFG_SEL 89
  99. #define CLK_TOP_MM_SEL 90
  100. #define CLK_TOP_PWM_SEL 91
  101. #define CLK_TOP_VDEC_SEL 92
  102. #define CLK_TOP_MFG_SEL 93
  103. #define CLK_TOP_CAMTG_SEL 94
  104. #define CLK_TOP_UART_SEL 95
  105. #define CLK_TOP_SPI0_SEL 96
  106. #define CLK_TOP_USB20_SEL 97
  107. #define CLK_TOP_MSDC30_0_SEL 98
  108. #define CLK_TOP_MSDC30_1_SEL 99
  109. #define CLK_TOP_MSDC30_2_SEL 100
  110. #define CLK_TOP_AUDIO_SEL 101
  111. #define CLK_TOP_AUDINTBUS_SEL 102
  112. #define CLK_TOP_PMICSPI_SEL 103
  113. #define CLK_TOP_SCP_SEL 104
  114. #define CLK_TOP_DPI0_SEL 105
  115. #define CLK_TOP_DPI1_SEL 106
  116. #define CLK_TOP_TVE_SEL 107
  117. #define CLK_TOP_HDMI_SEL 108
  118. #define CLK_TOP_APLL_SEL 109
  119. #define CLK_TOP_RTC_SEL 110
  120. #define CLK_TOP_NFI2X_SEL 111
  121. #define CLK_TOP_EMMC_HCLK_SEL 112
  122. #define CLK_TOP_FLASH_SEL 113
  123. #define CLK_TOP_DI_SEL 114
  124. #define CLK_TOP_NR_SEL 115
  125. #define CLK_TOP_OSD_SEL 116
  126. #define CLK_TOP_HDMIRX_BIST_SEL 117
  127. #define CLK_TOP_INTDIR_SEL 118
  128. #define CLK_TOP_ASM_I_SEL 119
  129. #define CLK_TOP_ASM_M_SEL 120
  130. #define CLK_TOP_ASM_H_SEL 121
  131. #define CLK_TOP_MS_CARD_SEL 122
  132. #define CLK_TOP_ETHIF_SEL 123
  133. #define CLK_TOP_HDMIRX26_24_SEL 124
  134. #define CLK_TOP_MSDC30_3_SEL 125
  135. #define CLK_TOP_CMSYS_SEL 126
  136. #define CLK_TOP_SPI1_SEL 127
  137. #define CLK_TOP_SPI2_SEL 128
  138. #define CLK_TOP_8BDAC_SEL 129
  139. #define CLK_TOP_AUD2DVD_SEL 130
  140. #define CLK_TOP_PADMCLK_SEL 131
  141. #define CLK_TOP_AUD_MUX1_SEL 132
  142. #define CLK_TOP_AUD_MUX2_SEL 133
  143. #define CLK_TOP_AUDPLL_MUX_SEL 134
  144. #define CLK_TOP_AUD_K1_SRC_SEL 135
  145. #define CLK_TOP_AUD_K2_SRC_SEL 136
  146. #define CLK_TOP_AUD_K3_SRC_SEL 137
  147. #define CLK_TOP_AUD_K4_SRC_SEL 138
  148. #define CLK_TOP_AUD_K5_SRC_SEL 139
  149. #define CLK_TOP_AUD_K6_SRC_SEL 140
  150. #define CLK_TOP_AUD_EXTCK1_DIV 141
  151. #define CLK_TOP_AUD_EXTCK2_DIV 142
  152. #define CLK_TOP_AUD_MUX1_DIV 143
  153. #define CLK_TOP_AUD_MUX2_DIV 144
  154. #define CLK_TOP_AUD_K1_SRC_DIV 145
  155. #define CLK_TOP_AUD_K2_SRC_DIV 146
  156. #define CLK_TOP_AUD_K3_SRC_DIV 147
  157. #define CLK_TOP_AUD_K4_SRC_DIV 148
  158. #define CLK_TOP_AUD_K5_SRC_DIV 149
  159. #define CLK_TOP_AUD_K6_SRC_DIV 150
  160. #define CLK_TOP_AUD_48K_TIMING 151
  161. #define CLK_TOP_AUD_44K_TIMING 152
  162. #define CLK_TOP_AUD_I2S1_MCLK 153
  163. #define CLK_TOP_AUD_I2S2_MCLK 154
  164. #define CLK_TOP_AUD_I2S3_MCLK 155
  165. #define CLK_TOP_AUD_I2S4_MCLK 156
  166. #define CLK_TOP_AUD_I2S5_MCLK 157
  167. #define CLK_TOP_AUD_I2S6_MCLK 158
  168. #define CLK_TOP_NR 159
  169. /* APMIXEDSYS */
  170. #define CLK_APMIXED_ARMPLL 0
  171. #define CLK_APMIXED_MAINPLL 1
  172. #define CLK_APMIXED_UNIVPLL 2
  173. #define CLK_APMIXED_MMPLL 3
  174. #define CLK_APMIXED_MSDCPLL 4
  175. #define CLK_APMIXED_TVDPLL 5
  176. #define CLK_APMIXED_AUD1PLL 6
  177. #define CLK_APMIXED_TRGPLL 7
  178. #define CLK_APMIXED_ETHPLL 8
  179. #define CLK_APMIXED_VDECPLL 9
  180. #define CLK_APMIXED_HADDS2PLL 10
  181. #define CLK_APMIXED_AUD2PLL 11
  182. #define CLK_APMIXED_TVD2PLL 12
  183. #define CLK_APMIXED_NR 13
  184. /* INFRACFG */
  185. #define CLK_INFRA_DBG 0
  186. #define CLK_INFRA_SMI 1
  187. #define CLK_INFRA_QAXI_CM4 2
  188. #define CLK_INFRA_AUD_SPLIN_B 3
  189. #define CLK_INFRA_AUDIO 4
  190. #define CLK_INFRA_EFUSE 5
  191. #define CLK_INFRA_L2C_SRAM 6
  192. #define CLK_INFRA_M4U 7
  193. #define CLK_INFRA_CONNMCU 8
  194. #define CLK_INFRA_TRNG 9
  195. #define CLK_INFRA_RAMBUFIF 10
  196. #define CLK_INFRA_CPUM 11
  197. #define CLK_INFRA_KP 12
  198. #define CLK_INFRA_CEC 13
  199. #define CLK_INFRA_IRRX 14
  200. #define CLK_INFRA_PMICSPI 15
  201. #define CLK_INFRA_PMICWRAP 16
  202. #define CLK_INFRA_DDCCI 17
  203. #define CLK_INFRA_CPUSEL 18
  204. #define CLK_INFRA_NR 19
  205. /* PERICFG */
  206. #define CLK_PERI_NFI 0
  207. #define CLK_PERI_THERM 1
  208. #define CLK_PERI_PWM1 2
  209. #define CLK_PERI_PWM2 3
  210. #define CLK_PERI_PWM3 4
  211. #define CLK_PERI_PWM4 5
  212. #define CLK_PERI_PWM5 6
  213. #define CLK_PERI_PWM6 7
  214. #define CLK_PERI_PWM7 8
  215. #define CLK_PERI_PWM 9
  216. #define CLK_PERI_USB0 10
  217. #define CLK_PERI_USB1 11
  218. #define CLK_PERI_AP_DMA 12
  219. #define CLK_PERI_MSDC30_0 13
  220. #define CLK_PERI_MSDC30_1 14
  221. #define CLK_PERI_MSDC30_2 15
  222. #define CLK_PERI_MSDC30_3 16
  223. #define CLK_PERI_MSDC50_3 17
  224. #define CLK_PERI_NLI 18
  225. #define CLK_PERI_UART0 19
  226. #define CLK_PERI_UART1 20
  227. #define CLK_PERI_UART2 21
  228. #define CLK_PERI_UART3 22
  229. #define CLK_PERI_BTIF 23
  230. #define CLK_PERI_I2C0 24
  231. #define CLK_PERI_I2C1 25
  232. #define CLK_PERI_I2C2 26
  233. #define CLK_PERI_I2C3 27
  234. #define CLK_PERI_AUXADC 28
  235. #define CLK_PERI_SPI0 39
  236. #define CLK_PERI_ETH 30
  237. #define CLK_PERI_USB0_MCU 31
  238. #define CLK_PERI_USB1_MCU 32
  239. #define CLK_PERI_USB_SLV 33
  240. #define CLK_PERI_GCPU 34
  241. #define CLK_PERI_NFI_ECC 35
  242. #define CLK_PERI_NFI_PAD 36
  243. #define CLK_PERI_FLASH 37
  244. #define CLK_PERI_HOST89_INT 38
  245. #define CLK_PERI_HOST89_SPI 39
  246. #define CLK_PERI_HOST89_DVD 40
  247. #define CLK_PERI_SPI1 41
  248. #define CLK_PERI_SPI2 42
  249. #define CLK_PERI_FCI 43
  250. #define CLK_PERI_NR 44
  251. /* AUDIO */
  252. #define CLK_AUD_AFE 0
  253. #define CLK_AUD_LRCK_DETECT 1
  254. #define CLK_AUD_I2S 2
  255. #define CLK_AUD_APLL_TUNER 3
  256. #define CLK_AUD_HDMI 4
  257. #define CLK_AUD_SPDF 5
  258. #define CLK_AUD_SPDF2 6
  259. #define CLK_AUD_APLL 7
  260. #define CLK_AUD_TML 8
  261. #define CLK_AUD_AHB_IDLE_EXT 9
  262. #define CLK_AUD_AHB_IDLE_INT 10
  263. #define CLK_AUD_I2SIN1 11
  264. #define CLK_AUD_I2SIN2 12
  265. #define CLK_AUD_I2SIN3 13
  266. #define CLK_AUD_I2SIN4 14
  267. #define CLK_AUD_I2SIN5 15
  268. #define CLK_AUD_I2SIN6 16
  269. #define CLK_AUD_I2SO1 17
  270. #define CLK_AUD_I2SO2 18
  271. #define CLK_AUD_I2SO3 19
  272. #define CLK_AUD_I2SO4 20
  273. #define CLK_AUD_I2SO5 21
  274. #define CLK_AUD_I2SO6 22
  275. #define CLK_AUD_ASRCI1 23
  276. #define CLK_AUD_ASRCI2 24
  277. #define CLK_AUD_ASRCO1 25
  278. #define CLK_AUD_ASRCO2 26
  279. #define CLK_AUD_ASRC11 27
  280. #define CLK_AUD_ASRC12 28
  281. #define CLK_AUD_HDMIRX 29
  282. #define CLK_AUD_INTDIR 30
  283. #define CLK_AUD_A1SYS 31
  284. #define CLK_AUD_A2SYS 32
  285. #define CLK_AUD_AFE_CONN 33
  286. #define CLK_AUD_AFE_PCMIF 34
  287. #define CLK_AUD_AFE_MRGIF 35
  288. #define CLK_AUD_MMIF_UL1 36
  289. #define CLK_AUD_MMIF_UL2 37
  290. #define CLK_AUD_MMIF_UL3 38
  291. #define CLK_AUD_MMIF_UL4 39
  292. #define CLK_AUD_MMIF_UL5 40
  293. #define CLK_AUD_MMIF_UL6 41
  294. #define CLK_AUD_MMIF_DL1 42
  295. #define CLK_AUD_MMIF_DL2 43
  296. #define CLK_AUD_MMIF_DL3 44
  297. #define CLK_AUD_MMIF_DL4 45
  298. #define CLK_AUD_MMIF_DL5 46
  299. #define CLK_AUD_MMIF_DL6 47
  300. #define CLK_AUD_MMIF_DLMCH 48
  301. #define CLK_AUD_MMIF_ARB1 49
  302. #define CLK_AUD_MMIF_AWB1 50
  303. #define CLK_AUD_MMIF_AWB2 51
  304. #define CLK_AUD_MMIF_DAI 52
  305. #define CLK_AUD_DMIC1 53
  306. #define CLK_AUD_DMIC2 54
  307. #define CLK_AUD_ASRCI3 55
  308. #define CLK_AUD_ASRCI4 56
  309. #define CLK_AUD_ASRCI5 57
  310. #define CLK_AUD_ASRCI6 58
  311. #define CLK_AUD_ASRCO3 59
  312. #define CLK_AUD_ASRCO4 60
  313. #define CLK_AUD_ASRCO5 61
  314. #define CLK_AUD_ASRCO6 62
  315. #define CLK_AUD_MEM_ASRC1 63
  316. #define CLK_AUD_MEM_ASRC2 64
  317. #define CLK_AUD_MEM_ASRC3 65
  318. #define CLK_AUD_MEM_ASRC4 66
  319. #define CLK_AUD_MEM_ASRC5 67
  320. #define CLK_AUD_DSD_ENC 68
  321. #define CLK_AUD_ASRC_BRG 60
  322. #define CLK_AUD_NR 70
  323. /* MMSYS */
  324. #define CLK_MM_SMI_COMMON 0
  325. #define CLK_MM_SMI_LARB0 1
  326. #define CLK_MM_CMDQ 2
  327. #define CLK_MM_MUTEX 3
  328. #define CLK_MM_DISP_COLOR 4
  329. #define CLK_MM_DISP_BLS 5
  330. #define CLK_MM_DISP_WDMA 6
  331. #define CLK_MM_DISP_RDMA 7
  332. #define CLK_MM_DISP_OVL 8
  333. #define CLK_MM_MDP_TDSHP 9
  334. #define CLK_MM_MDP_WROT 10
  335. #define CLK_MM_MDP_WDMA 11
  336. #define CLK_MM_MDP_RSZ1 12
  337. #define CLK_MM_MDP_RSZ0 13
  338. #define CLK_MM_MDP_RDMA 14
  339. #define CLK_MM_MDP_BLS_26M 15
  340. #define CLK_MM_CAM_MDP 16
  341. #define CLK_MM_FAKE_ENG 17
  342. #define CLK_MM_MUTEX_32K 18
  343. #define CLK_MM_DISP_RDMA1 19
  344. #define CLK_MM_DISP_UFOE 20
  345. #define CLK_MM_DSI_ENGINE 21
  346. #define CLK_MM_DSI_DIG 22
  347. #define CLK_MM_DPI_DIGL 23
  348. #define CLK_MM_DPI_ENGINE 24
  349. #define CLK_MM_DPI1_DIGL 25
  350. #define CLK_MM_DPI1_ENGINE 26
  351. #define CLK_MM_TVE_OUTPUT 27
  352. #define CLK_MM_TVE_INPUT 28
  353. #define CLK_MM_HDMI_PIXEL 29
  354. #define CLK_MM_HDMI_PLL 30
  355. #define CLK_MM_HDMI_AUDIO 31
  356. #define CLK_MM_HDMI_SPDIF 32
  357. #define CLK_MM_TVE_FMM 33
  358. #define CLK_MM_NR 34
  359. /* IMGSYS */
  360. #define CLK_IMG_SMI_COMM 0
  361. #define CLK_IMG_RESZ 1
  362. #define CLK_IMG_JPGDEC_SMI 2
  363. #define CLK_IMG_JPGDEC 3
  364. #define CLK_IMG_VENC_LT 4
  365. #define CLK_IMG_VENC 5
  366. #define CLK_IMG_NR 6
  367. /* VDEC */
  368. #define CLK_VDEC_CKGEN 0
  369. #define CLK_VDEC_LARB 1
  370. #define CLK_VDEC_NR 2
  371. /* HIFSYS */
  372. #define CLK_HIFSYS_USB0PHY 0
  373. #define CLK_HIFSYS_USB1PHY 1
  374. #define CLK_HIFSYS_PCIE0 2
  375. #define CLK_HIFSYS_PCIE1 3
  376. #define CLK_HIFSYS_PCIE2 4
  377. #define CLK_HIFSYS_NR 5
  378. /* ETHSYS */
  379. #define CLK_ETHSYS_HSDMA 0
  380. #define CLK_ETHSYS_ESW 1
  381. #define CLK_ETHSYS_GP2 2
  382. #define CLK_ETHSYS_GP1 3
  383. #define CLK_ETHSYS_PCM 4
  384. #define CLK_ETHSYS_GDMA 5
  385. #define CLK_ETHSYS_I2S 6
  386. #define CLK_ETHSYS_CRYPTO 7
  387. #define CLK_ETHSYS_NR 8
  388. /* G3DSYS */
  389. #define CLK_G3DSYS_CORE 0
  390. #define CLK_G3DSYS_NR 1
  391. #endif /* _DT_BINDINGS_CLK_MT2701_H */