imx8mq-clock.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017 NXP
  5. */
  6. #ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
  7. #define __DT_BINDINGS_CLOCK_IMX8MQ_H
  8. #define IMX8MQ_CLK_DUMMY 0
  9. #define IMX8MQ_CLK_32K 1
  10. #define IMX8MQ_CLK_25M 2
  11. #define IMX8MQ_CLK_27M 3
  12. #define IMX8MQ_CLK_EXT1 4
  13. #define IMX8MQ_CLK_EXT2 5
  14. #define IMX8MQ_CLK_EXT3 6
  15. #define IMX8MQ_CLK_EXT4 7
  16. /* ANAMIX PLL clocks */
  17. /* FRAC PLLs */
  18. /* ARM PLL */
  19. #define IMX8MQ_ARM_PLL_REF_SEL 8
  20. #define IMX8MQ_ARM_PLL_REF_DIV 9
  21. #define IMX8MQ_ARM_PLL 10
  22. #define IMX8MQ_ARM_PLL_BYPASS 11
  23. #define IMX8MQ_ARM_PLL_OUT 12
  24. /* GPU PLL */
  25. #define IMX8MQ_GPU_PLL_REF_SEL 13
  26. #define IMX8MQ_GPU_PLL_REF_DIV 14
  27. #define IMX8MQ_GPU_PLL 15
  28. #define IMX8MQ_GPU_PLL_BYPASS 16
  29. #define IMX8MQ_GPU_PLL_OUT 17
  30. /* VPU PLL */
  31. #define IMX8MQ_VPU_PLL_REF_SEL 18
  32. #define IMX8MQ_VPU_PLL_REF_DIV 19
  33. #define IMX8MQ_VPU_PLL 20
  34. #define IMX8MQ_VPU_PLL_BYPASS 21
  35. #define IMX8MQ_VPU_PLL_OUT 22
  36. /* AUDIO PLL1 */
  37. #define IMX8MQ_AUDIO_PLL1_REF_SEL 23
  38. #define IMX8MQ_AUDIO_PLL1_REF_DIV 24
  39. #define IMX8MQ_AUDIO_PLL1 25
  40. #define IMX8MQ_AUDIO_PLL1_BYPASS 26
  41. #define IMX8MQ_AUDIO_PLL1_OUT 27
  42. /* AUDIO PLL2 */
  43. #define IMX8MQ_AUDIO_PLL2_REF_SEL 28
  44. #define IMX8MQ_AUDIO_PLL2_REF_DIV 29
  45. #define IMX8MQ_AUDIO_PLL2 30
  46. #define IMX8MQ_AUDIO_PLL2_BYPASS 31
  47. #define IMX8MQ_AUDIO_PLL2_OUT 32
  48. /* VIDEO PLL1 */
  49. #define IMX8MQ_VIDEO_PLL1_REF_SEL 33
  50. #define IMX8MQ_VIDEO_PLL1_REF_DIV 34
  51. #define IMX8MQ_VIDEO_PLL1 35
  52. #define IMX8MQ_VIDEO_PLL1_BYPASS 36
  53. #define IMX8MQ_VIDEO_PLL1_OUT 37
  54. /* SYS1 PLL */
  55. #define IMX8MQ_SYS1_PLL1_REF_SEL 38
  56. #define IMX8MQ_SYS1_PLL1_REF_DIV 39
  57. #define IMX8MQ_SYS1_PLL1 40
  58. #define IMX8MQ_SYS1_PLL1_OUT 41
  59. #define IMX8MQ_SYS1_PLL1_OUT_DIV 42
  60. #define IMX8MQ_SYS1_PLL2 43
  61. #define IMX8MQ_SYS1_PLL2_DIV 44
  62. #define IMX8MQ_SYS1_PLL2_OUT 45
  63. /* SYS2 PLL */
  64. #define IMX8MQ_SYS2_PLL1_REF_SEL 46
  65. #define IMX8MQ_SYS2_PLL1_REF_DIV 47
  66. #define IMX8MQ_SYS2_PLL1 48
  67. #define IMX8MQ_SYS2_PLL1_OUT 49
  68. #define IMX8MQ_SYS2_PLL1_OUT_DIV 50
  69. #define IMX8MQ_SYS2_PLL2 51
  70. #define IMX8MQ_SYS2_PLL2_DIV 52
  71. #define IMX8MQ_SYS2_PLL2_OUT 53
  72. /* SYS3 PLL */
  73. #define IMX8MQ_SYS3_PLL1_REF_SEL 54
  74. #define IMX8MQ_SYS3_PLL1_REF_DIV 55
  75. #define IMX8MQ_SYS3_PLL1 56
  76. #define IMX8MQ_SYS3_PLL1_OUT 57
  77. #define IMX8MQ_SYS3_PLL1_OUT_DIV 58
  78. #define IMX8MQ_SYS3_PLL2 59
  79. #define IMX8MQ_SYS3_PLL2_DIV 60
  80. #define IMX8MQ_SYS3_PLL2_OUT 61
  81. /* DRAM PLL */
  82. #define IMX8MQ_DRAM_PLL1_REF_SEL 62
  83. #define IMX8MQ_DRAM_PLL1_REF_DIV 63
  84. #define IMX8MQ_DRAM_PLL1 64
  85. #define IMX8MQ_DRAM_PLL1_OUT 65
  86. #define IMX8MQ_DRAM_PLL1_OUT_DIV 66
  87. #define IMX8MQ_DRAM_PLL2 67
  88. #define IMX8MQ_DRAM_PLL2_DIV 68
  89. #define IMX8MQ_DRAM_PLL2_OUT 69
  90. /* SYS PLL DIV */
  91. #define IMX8MQ_SYS1_PLL_40M 70
  92. #define IMX8MQ_SYS1_PLL_80M 71
  93. #define IMX8MQ_SYS1_PLL_100M 72
  94. #define IMX8MQ_SYS1_PLL_133M 73
  95. #define IMX8MQ_SYS1_PLL_160M 74
  96. #define IMX8MQ_SYS1_PLL_200M 75
  97. #define IMX8MQ_SYS1_PLL_266M 76
  98. #define IMX8MQ_SYS1_PLL_400M 77
  99. #define IMX8MQ_SYS1_PLL_800M 78
  100. #define IMX8MQ_SYS2_PLL_50M 79
  101. #define IMX8MQ_SYS2_PLL_100M 80
  102. #define IMX8MQ_SYS2_PLL_125M 81
  103. #define IMX8MQ_SYS2_PLL_166M 82
  104. #define IMX8MQ_SYS2_PLL_200M 83
  105. #define IMX8MQ_SYS2_PLL_250M 84
  106. #define IMX8MQ_SYS2_PLL_333M 85
  107. #define IMX8MQ_SYS2_PLL_500M 86
  108. #define IMX8MQ_SYS2_PLL_1000M 87
  109. /* CCM ROOT clocks */
  110. /* A53 */
  111. #define IMX8MQ_CLK_A53_SRC 88
  112. #define IMX8MQ_CLK_A53_CG 89
  113. #define IMX8MQ_CLK_A53_DIV 90
  114. /* M4 */
  115. #define IMX8MQ_CLK_M4_SRC 91
  116. #define IMX8MQ_CLK_M4_CG 92
  117. #define IMX8MQ_CLK_M4_DIV 93
  118. /* VPU */
  119. #define IMX8MQ_CLK_VPU_SRC 94
  120. #define IMX8MQ_CLK_VPU_CG 95
  121. #define IMX8MQ_CLK_VPU_DIV 96
  122. /* GPU CORE */
  123. #define IMX8MQ_CLK_GPU_CORE_SRC 97
  124. #define IMX8MQ_CLK_GPU_CORE_CG 98
  125. #define IMX8MQ_CLK_GPU_CORE_DIV 99
  126. /* GPU SHADER */
  127. #define IMX8MQ_CLK_GPU_SHADER_SRC 100
  128. #define IMX8MQ_CLK_GPU_SHADER_CG 101
  129. #define IMX8MQ_CLK_GPU_SHADER_DIV 102
  130. /* BUS TYPE */
  131. /* MAIN AXI */
  132. #define IMX8MQ_CLK_MAIN_AXI 103
  133. /* ENET AXI */
  134. #define IMX8MQ_CLK_ENET_AXI 104
  135. /* NAND_USDHC_BUS */
  136. #define IMX8MQ_CLK_NAND_USDHC_BUS 105
  137. /* VPU BUS */
  138. #define IMX8MQ_CLK_VPU_BUS 106
  139. /* DISP_AXI */
  140. #define IMX8MQ_CLK_DISP_AXI 107
  141. /* DISP APB */
  142. #define IMX8MQ_CLK_DISP_APB 108
  143. /* DISP RTRM */
  144. #define IMX8MQ_CLK_DISP_RTRM 109
  145. /* USB_BUS */
  146. #define IMX8MQ_CLK_USB_BUS 110
  147. /* GPU_AXI */
  148. #define IMX8MQ_CLK_GPU_AXI 111
  149. /* GPU_AHB */
  150. #define IMX8MQ_CLK_GPU_AHB 112
  151. /* NOC */
  152. #define IMX8MQ_CLK_NOC 113
  153. /* NOC_APB */
  154. #define IMX8MQ_CLK_NOC_APB 115
  155. /* AHB */
  156. #define IMX8MQ_CLK_AHB 116
  157. /* AUDIO AHB */
  158. #define IMX8MQ_CLK_AUDIO_AHB 117
  159. /* DRAM_ALT */
  160. #define IMX8MQ_CLK_DRAM_ALT 118
  161. /* DRAM APB */
  162. #define IMX8MQ_CLK_DRAM_APB 119
  163. /* VPU_G1 */
  164. #define IMX8MQ_CLK_VPU_G1 120
  165. /* VPU_G2 */
  166. #define IMX8MQ_CLK_VPU_G2 121
  167. /* DISP_DTRC */
  168. #define IMX8MQ_CLK_DISP_DTRC 122
  169. /* DISP_DC8000 */
  170. #define IMX8MQ_CLK_DISP_DC8000 123
  171. /* PCIE_CTRL */
  172. #define IMX8MQ_CLK_PCIE1_CTRL 124
  173. /* PCIE_PHY */
  174. #define IMX8MQ_CLK_PCIE1_PHY 125
  175. /* PCIE_AUX */
  176. #define IMX8MQ_CLK_PCIE1_AUX 126
  177. /* DC_PIXEL */
  178. #define IMX8MQ_CLK_DC_PIXEL 127
  179. /* LCDIF_PIXEL */
  180. #define IMX8MQ_CLK_LCDIF_PIXEL 128
  181. /* SAI1~6 */
  182. #define IMX8MQ_CLK_SAI1 129
  183. #define IMX8MQ_CLK_SAI2 130
  184. #define IMX8MQ_CLK_SAI3 131
  185. #define IMX8MQ_CLK_SAI4 132
  186. #define IMX8MQ_CLK_SAI5 133
  187. #define IMX8MQ_CLK_SAI6 134
  188. /* SPDIF1 */
  189. #define IMX8MQ_CLK_SPDIF1 135
  190. /* SPDIF2 */
  191. #define IMX8MQ_CLK_SPDIF2 136
  192. /* ENET_REF */
  193. #define IMX8MQ_CLK_ENET_REF 137
  194. /* ENET_TIMER */
  195. #define IMX8MQ_CLK_ENET_TIMER 138
  196. /* ENET_PHY */
  197. #define IMX8MQ_CLK_ENET_PHY_REF 139
  198. /* NAND */
  199. #define IMX8MQ_CLK_NAND 140
  200. /* QSPI */
  201. #define IMX8MQ_CLK_QSPI 141
  202. /* USDHC1 */
  203. #define IMX8MQ_CLK_USDHC1 142
  204. /* USDHC2 */
  205. #define IMX8MQ_CLK_USDHC2 143
  206. /* I2C1 */
  207. #define IMX8MQ_CLK_I2C1 144
  208. /* I2C2 */
  209. #define IMX8MQ_CLK_I2C2 145
  210. /* I2C3 */
  211. #define IMX8MQ_CLK_I2C3 146
  212. /* I2C4 */
  213. #define IMX8MQ_CLK_I2C4 147
  214. /* UART1 */
  215. #define IMX8MQ_CLK_UART1 148
  216. /* UART2 */
  217. #define IMX8MQ_CLK_UART2 149
  218. /* UART3 */
  219. #define IMX8MQ_CLK_UART3 150
  220. /* UART4 */
  221. #define IMX8MQ_CLK_UART4 151
  222. /* USB_CORE_REF */
  223. #define IMX8MQ_CLK_USB_CORE_REF 152
  224. /* USB_PHY_REF */
  225. #define IMX8MQ_CLK_USB_PHY_REF 153
  226. /* ECSPI1 */
  227. #define IMX8MQ_CLK_ECSPI1 154
  228. /* ECSPI2 */
  229. #define IMX8MQ_CLK_ECSPI2 155
  230. /* PWM1 */
  231. #define IMX8MQ_CLK_PWM1 156
  232. /* PWM2 */
  233. #define IMX8MQ_CLK_PWM2 157
  234. /* PWM3 */
  235. #define IMX8MQ_CLK_PWM3 158
  236. /* PWM4 */
  237. #define IMX8MQ_CLK_PWM4 159
  238. /* GPT1 */
  239. #define IMX8MQ_CLK_GPT1 160
  240. /* WDOG */
  241. #define IMX8MQ_CLK_WDOG 161
  242. /* WRCLK */
  243. #define IMX8MQ_CLK_WRCLK 162
  244. /* DSI_CORE */
  245. #define IMX8MQ_CLK_DSI_CORE 163
  246. /* DSI_PHY */
  247. #define IMX8MQ_CLK_DSI_PHY_REF 164
  248. /* DSI_DBI */
  249. #define IMX8MQ_CLK_DSI_DBI 165
  250. /*DSI_ESC */
  251. #define IMX8MQ_CLK_DSI_ESC 166
  252. /* CSI1_CORE */
  253. #define IMX8MQ_CLK_CSI1_CORE 167
  254. /* CSI1_PHY */
  255. #define IMX8MQ_CLK_CSI1_PHY_REF 168
  256. /* CSI_ESC */
  257. #define IMX8MQ_CLK_CSI1_ESC 169
  258. /* CSI2_CORE */
  259. #define IMX8MQ_CLK_CSI2_CORE 170
  260. /* CSI2_PHY */
  261. #define IMX8MQ_CLK_CSI2_PHY_REF 171
  262. /* CSI2_ESC */
  263. #define IMX8MQ_CLK_CSI2_ESC 172
  264. /* PCIE2_CTRL */
  265. #define IMX8MQ_CLK_PCIE2_CTRL 173
  266. /* PCIE2_PHY */
  267. #define IMX8MQ_CLK_PCIE2_PHY 174
  268. /* PCIE2_AUX */
  269. #define IMX8MQ_CLK_PCIE2_AUX 175
  270. /* ECSPI3 */
  271. #define IMX8MQ_CLK_ECSPI3 176
  272. /* CCGR clocks */
  273. #define IMX8MQ_CLK_A53_ROOT 177
  274. #define IMX8MQ_CLK_DRAM_ROOT 178
  275. #define IMX8MQ_CLK_ECSPI1_ROOT 179
  276. #define IMX8MQ_CLK_ECSPI2_ROOT 180
  277. #define IMX8MQ_CLK_ECSPI3_ROOT 181
  278. #define IMX8MQ_CLK_ENET1_ROOT 182
  279. #define IMX8MQ_CLK_GPT1_ROOT 183
  280. #define IMX8MQ_CLK_I2C1_ROOT 184
  281. #define IMX8MQ_CLK_I2C2_ROOT 185
  282. #define IMX8MQ_CLK_I2C3_ROOT 186
  283. #define IMX8MQ_CLK_I2C4_ROOT 187
  284. #define IMX8MQ_CLK_M4_ROOT 188
  285. #define IMX8MQ_CLK_PCIE1_ROOT 189
  286. #define IMX8MQ_CLK_PCIE2_ROOT 190
  287. #define IMX8MQ_CLK_PWM1_ROOT 191
  288. #define IMX8MQ_CLK_PWM2_ROOT 192
  289. #define IMX8MQ_CLK_PWM3_ROOT 193
  290. #define IMX8MQ_CLK_PWM4_ROOT 194
  291. #define IMX8MQ_CLK_QSPI_ROOT 195
  292. #define IMX8MQ_CLK_SAI1_ROOT 196
  293. #define IMX8MQ_CLK_SAI2_ROOT 197
  294. #define IMX8MQ_CLK_SAI3_ROOT 198
  295. #define IMX8MQ_CLK_SAI4_ROOT 199
  296. #define IMX8MQ_CLK_SAI5_ROOT 200
  297. #define IMX8MQ_CLK_SAI6_ROOT 201
  298. #define IMX8MQ_CLK_UART1_ROOT 202
  299. #define IMX8MQ_CLK_UART2_ROOT 203
  300. #define IMX8MQ_CLK_UART3_ROOT 204
  301. #define IMX8MQ_CLK_UART4_ROOT 205
  302. #define IMX8MQ_CLK_USB1_CTRL_ROOT 206
  303. #define IMX8MQ_CLK_USB2_CTRL_ROOT 207
  304. #define IMX8MQ_CLK_USB1_PHY_ROOT 208
  305. #define IMX8MQ_CLK_USB2_PHY_ROOT 209
  306. #define IMX8MQ_CLK_USDHC1_ROOT 210
  307. #define IMX8MQ_CLK_USDHC2_ROOT 211
  308. #define IMX8MQ_CLK_WDOG1_ROOT 212
  309. #define IMX8MQ_CLK_WDOG2_ROOT 213
  310. #define IMX8MQ_CLK_WDOG3_ROOT 214
  311. #define IMX8MQ_CLK_GPU_ROOT 215
  312. #define IMX8MQ_CLK_HEVC_ROOT 216
  313. #define IMX8MQ_CLK_AVC_ROOT 217
  314. #define IMX8MQ_CLK_VP9_ROOT 218
  315. #define IMX8MQ_CLK_HEVC_INTER_ROOT 219
  316. #define IMX8MQ_CLK_DISP_ROOT 220
  317. #define IMX8MQ_CLK_HDMI_ROOT 221
  318. #define IMX8MQ_CLK_HDMI_PHY_ROOT 222
  319. #define IMX8MQ_CLK_VPU_DEC_ROOT 223
  320. #define IMX8MQ_CLK_CSI1_ROOT 224
  321. #define IMX8MQ_CLK_CSI2_ROOT 225
  322. #define IMX8MQ_CLK_RAWNAND_ROOT 226
  323. #define IMX8MQ_CLK_SDMA1_ROOT 227
  324. #define IMX8MQ_CLK_SDMA2_ROOT 228
  325. #define IMX8MQ_CLK_VPU_G1_ROOT 229
  326. #define IMX8MQ_CLK_VPU_G2_ROOT 230
  327. /* SCCG PLL GATE */
  328. #define IMX8MQ_SYS1_PLL_OUT 231
  329. #define IMX8MQ_SYS2_PLL_OUT 232
  330. #define IMX8MQ_SYS3_PLL_OUT 233
  331. #define IMX8MQ_DRAM_PLL_OUT 234
  332. #define IMX8MQ_GPT_3M_CLK 235
  333. #define IMX8MQ_CLK_IPG_ROOT 236
  334. #define IMX8MQ_CLK_IPG_AUDIO_ROOT 237
  335. #define IMX8MQ_CLK_SAI1_IPG 238
  336. #define IMX8MQ_CLK_SAI2_IPG 239
  337. #define IMX8MQ_CLK_SAI3_IPG 240
  338. #define IMX8MQ_CLK_SAI4_IPG 241
  339. #define IMX8MQ_CLK_SAI5_IPG 242
  340. #define IMX8MQ_CLK_SAI6_IPG 243
  341. /* DSI AHB/IPG clocks */
  342. /* rxesc clock */
  343. #define IMX8MQ_CLK_DSI_AHB 244
  344. /* txesc clock */
  345. #define IMX8MQ_CLK_DSI_IPG_DIV 245
  346. #define IMX8MQ_CLK_TMU_ROOT 246
  347. /* Display root clocks */
  348. #define IMX8MQ_CLK_DISP_AXI_ROOT 247
  349. #define IMX8MQ_CLK_DISP_APB_ROOT 248
  350. #define IMX8MQ_CLK_DISP_RTRM_ROOT 249
  351. #define IMX8MQ_CLK_OCOTP_ROOT 250
  352. #define IMX8MQ_CLK_DRAM_ALT_ROOT 251
  353. #define IMX8MQ_CLK_DRAM_CORE 252
  354. #define IMX8MQ_CLK_MU_ROOT 253
  355. #define IMX8MQ_VIDEO2_PLL_OUT 254
  356. #define IMX8MQ_CLK_CLKO2 255
  357. #define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256
  358. #define IMX8MQ_CLK_CLKO1 257
  359. #define IMX8MQ_CLK_ARM 258
  360. #define IMX8MQ_CLK_GPIO1_ROOT 259
  361. #define IMX8MQ_CLK_GPIO2_ROOT 260
  362. #define IMX8MQ_CLK_GPIO3_ROOT 261
  363. #define IMX8MQ_CLK_GPIO4_ROOT 262
  364. #define IMX8MQ_CLK_GPIO5_ROOT 263
  365. #define IMX8MQ_CLK_SNVS_ROOT 264
  366. #define IMX8MQ_CLK_GIC 265
  367. #define IMX8MQ_CLK_END 266
  368. #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */