imx7ulp-clock.h 4.8 KB

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  1. /*
  2. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. */
  9. #ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
  10. #define __DT_BINDINGS_CLOCK_IMX7ULP_H
  11. #define IMX7ULP_CLK_DUMMY 0
  12. #define IMX7ULP_CLK_CKIL 1
  13. #define IMX7ULP_CLK_OSC 2
  14. #define IMX7ULP_CLK_FIRC 3
  15. /* SCG1 */
  16. #define IMX7ULP_CLK_SPLL_PRE_SEL 4
  17. #define IMX7ULP_CLK_SPLL_PRE_DIV 5
  18. #define IMX7ULP_CLK_SPLL 6
  19. #define IMX7ULP_CLK_SPLL_POST_DIV1 7
  20. #define IMX7ULP_CLK_SPLL_POST_DIV2 8
  21. #define IMX7ULP_CLK_SPLL_PFD0 9
  22. #define IMX7ULP_CLK_SPLL_PFD1 10
  23. #define IMX7ULP_CLK_SPLL_PFD2 11
  24. #define IMX7ULP_CLK_SPLL_PFD3 12
  25. #define IMX7ULP_CLK_SPLL_PFD_SEL 13
  26. #define IMX7ULP_CLK_SPLL_SEL 14
  27. #define IMX7ULP_CLK_APLL_PRE_SEL 15
  28. #define IMX7ULP_CLK_APLL_PRE_DIV 16
  29. #define IMX7ULP_CLK_APLL 17
  30. #define IMX7ULP_CLK_APLL_POST_DIV1 18
  31. #define IMX7ULP_CLK_APLL_POST_DIV2 19
  32. #define IMX7ULP_CLK_APLL_PFD0 20
  33. #define IMX7ULP_CLK_APLL_PFD1 21
  34. #define IMX7ULP_CLK_APLL_PFD2 22
  35. #define IMX7ULP_CLK_APLL_PFD3 23
  36. #define IMX7ULP_CLK_APLL_PFD_SEL 24
  37. #define IMX7ULP_CLK_APLL_SEL 25
  38. #define IMX7ULP_CLK_UPLL 26
  39. #define IMX7ULP_CLK_SYS_SEL 27
  40. #define IMX7ULP_CLK_CORE_DIV 28
  41. #define IMX7ULP_CLK_BUS_DIV 29
  42. #define IMX7ULP_CLK_PLAT_DIV 30
  43. #define IMX7ULP_CLK_DDR_SEL 31
  44. #define IMX7ULP_CLK_DDR_DIV 32
  45. #define IMX7ULP_CLK_NIC_SEL 33
  46. #define IMX7ULP_CLK_NIC0_DIV 34
  47. #define IMX7ULP_CLK_GPU_DIV 35
  48. #define IMX7ULP_CLK_NIC1_DIV 36
  49. #define IMX7ULP_CLK_NIC1_BUS_DIV 37
  50. #define IMX7ULP_CLK_NIC1_EXT_DIV 38
  51. /* PCG2 */
  52. #define IMX7ULP_CLK_DMA1 39
  53. #define IMX7ULP_CLK_RGPIO2P1 40
  54. #define IMX7ULP_CLK_FLEXBUS 41
  55. #define IMX7ULP_CLK_SEMA42_1 42
  56. #define IMX7ULP_CLK_DMA_MUX1 43
  57. #define IMX7ULP_CLK_SNVS 44
  58. #define IMX7ULP_CLK_CAAM 45
  59. #define IMX7ULP_CLK_LPTPM4 46
  60. #define IMX7ULP_CLK_LPTPM5 47
  61. #define IMX7ULP_CLK_LPIT1 48
  62. #define IMX7ULP_CLK_LPSPI2 49
  63. #define IMX7ULP_CLK_LPSPI3 50
  64. #define IMX7ULP_CLK_LPI2C4 51
  65. #define IMX7ULP_CLK_LPI2C5 52
  66. #define IMX7ULP_CLK_LPUART4 53
  67. #define IMX7ULP_CLK_LPUART5 54
  68. #define IMX7ULP_CLK_FLEXIO1 55
  69. #define IMX7ULP_CLK_USB0 56
  70. #define IMX7ULP_CLK_USB1 57
  71. #define IMX7ULP_CLK_USB_PHY 58
  72. #define IMX7ULP_CLK_USB_PL301 59
  73. #define IMX7ULP_CLK_USDHC0 60
  74. #define IMX7ULP_CLK_USDHC1 61
  75. #define IMX7ULP_CLK_WDG1 62
  76. #define IMX7ULP_CLK_WDG2 63
  77. /* PCG3 */
  78. #define IMX7ULP_CLK_LPTPM6 64
  79. #define IMX7ULP_CLK_LPTPM7 65
  80. #define IMX7ULP_CLK_LPI2C6 66
  81. #define IMX7ULP_CLK_LPI2C7 67
  82. #define IMX7ULP_CLK_LPUART6 68
  83. #define IMX7ULP_CLK_LPUART7 69
  84. #define IMX7ULP_CLK_VIU 70
  85. #define IMX7ULP_CLK_DSI 71
  86. #define IMX7ULP_CLK_LCDIF 72
  87. #define IMX7ULP_CLK_MMDC 73
  88. #define IMX7ULP_CLK_PCTLC 74
  89. #define IMX7ULP_CLK_PCTLD 75
  90. #define IMX7ULP_CLK_PCTLE 76
  91. #define IMX7ULP_CLK_PCTLF 77
  92. #define IMX7ULP_CLK_GPU3D 78
  93. #define IMX7ULP_CLK_GPU2D 79
  94. #define IMX7ULP_CLK_MIPI_PLL 80
  95. #define IMX7ULP_CLK_SIRC 81
  96. #define IMX7ULP_CLK_SCG1_CLKOUT 82
  97. #define IMX7ULP_CLK_END 83
  98. /*cm4 clocks*/
  99. #define IMX7ULP_CM4_CLK_DUMMY 0
  100. #define IMX7ULP_CM4_CLK_CKIL 1
  101. #define IMX7ULP_CM4_CLK_OSC 2
  102. #define IMX7ULP_CM4_CLK_FIRC 3
  103. #define IMX7ULP_CM4_CLK_SIRC 4
  104. /* SCG0 */
  105. #define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL 5
  106. #define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV 6
  107. #define IMX7ULP_CM4_CLK_SPLL 7
  108. #define IMX7ULP_CM4_CLK_SPLL_VCO 8
  109. #define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1 9
  110. #define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2 10
  111. #define IMX7ULP_CM4_CLK_SPLL_PFD0 11
  112. #define IMX7ULP_CM4_CLK_SPLL_PFD1 12
  113. #define IMX7ULP_CM4_CLK_SPLL_PFD2 13
  114. #define IMX7ULP_CM4_CLK_SPLL_PFD3 14
  115. #define IMX7ULP_CM4_CLK_SPLL_PFD_SEL 15
  116. #define IMX7ULP_CM4_CLK_SPLL_PFD 16
  117. #define IMX7ULP_CM4_CLK_SPLL_SEL 17
  118. #define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL 18
  119. #define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV 19
  120. #define IMX7ULP_CM4_CLK_APLL 20
  121. #define IMX7ULP_CM4_CLK_APLL_VCO 21
  122. #define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1 22
  123. #define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2 23
  124. #define IMX7ULP_CM4_CLK_APLL_PFD0 24
  125. #define IMX7ULP_CM4_CLK_APLL_PFD1 25
  126. #define IMX7ULP_CM4_CLK_APLL_PFD2 26
  127. #define IMX7ULP_CM4_CLK_APLL_PFD3 27
  128. #define IMX7ULP_CM4_CLK_APLL_PFD_SEL 28
  129. #define IMX7ULP_CM4_CLK_APLL_PFD 29
  130. #define IMX7ULP_CM4_CLK_APLL_SEL 30
  131. #define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV 31
  132. #define IMX7ULP_CM4_CLK_SYS_SEL 32
  133. #define IMX7ULP_CM4_CLK_CORE_DIV 33
  134. #define IMX7ULP_CM4_CLK_BUS_DIV 34
  135. #define IMX7ULP_CM4_CLK_PLAT_DIV 35
  136. #define IMX7ULP_CM4_CLK_SLOW_DIV 36
  137. #define IMX7ULP_CM4_CLK_SAI0_SEL 37
  138. #define IMX7ULP_CM4_CLK_SAI0_DIV 38
  139. #define IMX7ULP_CM4_CLK_SAI0_ROOT 39
  140. #define IMX7ULP_CM4_CLK_SAI0_IPG 40
  141. #define IMX7ULP_CM4_CLK_SAI1_SEL 41
  142. #define IMX7ULP_CM4_CLK_SAI1_DIV 42
  143. #define IMX7ULP_CM4_CLK_SAI1_ROOT 43
  144. #define IMX7ULP_CM4_CLK_SAI1_IPG 44
  145. #define IMX7ULP_CLK_SCG0_CLKOUT 45
  146. #define IMX7ULP_CM4_CLK_END 46
  147. #endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */