g12a-clkc.h 4.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ OR MIT */
  2. /*
  3. * Meson-G12A clock tree IDs
  4. *
  5. * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
  6. */
  7. #ifndef __G12A_CLKC_H
  8. #define __G12A_CLKC_H
  9. #define CLKID_SYS_PLL 0
  10. #define CLKID_FIXED_PLL 1
  11. #define CLKID_FCLK_DIV2 2
  12. #define CLKID_FCLK_DIV3 3
  13. #define CLKID_FCLK_DIV4 4
  14. #define CLKID_FCLK_DIV5 5
  15. #define CLKID_FCLK_DIV7 6
  16. #define CLKID_GP0_PLL 7
  17. #define CLKID_CLK81 10
  18. #define CLKID_MPLL0 11
  19. #define CLKID_MPLL1 12
  20. #define CLKID_MPLL2 13
  21. #define CLKID_MPLL3 14
  22. #define CLKID_DDR 15
  23. #define CLKID_DOS 16
  24. #define CLKID_AUDIO_LOCKER 17
  25. #define CLKID_MIPI_DSI_HOST 18
  26. #define CLKID_ETH_PHY 19
  27. #define CLKID_ISA 20
  28. #define CLKID_PL301 21
  29. #define CLKID_PERIPHS 22
  30. #define CLKID_SPICC0 23
  31. #define CLKID_I2C 24
  32. #define CLKID_SANA 25
  33. #define CLKID_SD 26
  34. #define CLKID_RNG0 27
  35. #define CLKID_UART0 28
  36. #define CLKID_SPICC1 29
  37. #define CLKID_HIU_IFACE 30
  38. #define CLKID_MIPI_DSI_PHY 31
  39. #define CLKID_ASSIST_MISC 32
  40. #define CLKID_SD_EMMC_A 33
  41. #define CLKID_SD_EMMC_B 34
  42. #define CLKID_SD_EMMC_C 35
  43. #define CLKID_AUDIO_CODEC 36
  44. #define CLKID_AUDIO 37
  45. #define CLKID_ETH 38
  46. #define CLKID_DEMUX 39
  47. #define CLKID_AUDIO_IFIFO 40
  48. #define CLKID_ADC 41
  49. #define CLKID_UART1 42
  50. #define CLKID_G2D 43
  51. #define CLKID_RESET 44
  52. #define CLKID_PCIE_COMB 45
  53. #define CLKID_PARSER 46
  54. #define CLKID_USB 47
  55. #define CLKID_PCIE_PHY 48
  56. #define CLKID_AHB_ARB0 49
  57. #define CLKID_AHB_DATA_BUS 50
  58. #define CLKID_AHB_CTRL_BUS 51
  59. #define CLKID_HTX_HDCP22 52
  60. #define CLKID_HTX_PCLK 53
  61. #define CLKID_BT656 54
  62. #define CLKID_USB1_DDR_BRIDGE 55
  63. #define CLKID_MMC_PCLK 56
  64. #define CLKID_UART2 57
  65. #define CLKID_VPU_INTR 58
  66. #define CLKID_GIC 59
  67. #define CLKID_SD_EMMC_A_CLK0 60
  68. #define CLKID_SD_EMMC_B_CLK0 61
  69. #define CLKID_SD_EMMC_C_CLK0 62
  70. #define CLKID_HIFI_PLL 74
  71. #define CLKID_VCLK2_VENCI0 80
  72. #define CLKID_VCLK2_VENCI1 81
  73. #define CLKID_VCLK2_VENCP0 82
  74. #define CLKID_VCLK2_VENCP1 83
  75. #define CLKID_VCLK2_VENCT0 84
  76. #define CLKID_VCLK2_VENCT1 85
  77. #define CLKID_VCLK2_OTHER 86
  78. #define CLKID_VCLK2_ENCI 87
  79. #define CLKID_VCLK2_ENCP 88
  80. #define CLKID_DAC_CLK 89
  81. #define CLKID_AOCLK 90
  82. #define CLKID_IEC958 91
  83. #define CLKID_ENC480P 92
  84. #define CLKID_RNG1 93
  85. #define CLKID_VCLK2_ENCT 94
  86. #define CLKID_VCLK2_ENCL 95
  87. #define CLKID_VCLK2_VENCLMMC 96
  88. #define CLKID_VCLK2_VENCL 97
  89. #define CLKID_VCLK2_OTHER1 98
  90. #define CLKID_FCLK_DIV2P5 99
  91. #define CLKID_DMA 105
  92. #define CLKID_EFUSE 106
  93. #define CLKID_ROM_BOOT 107
  94. #define CLKID_RESET_SEC 108
  95. #define CLKID_SEC_AHB_APB3 109
  96. #define CLKID_VPU_0_SEL 110
  97. #define CLKID_VPU_0 112
  98. #define CLKID_VPU_1_SEL 113
  99. #define CLKID_VPU_1 115
  100. #define CLKID_VPU 116
  101. #define CLKID_VAPB_0_SEL 117
  102. #define CLKID_VAPB_0 119
  103. #define CLKID_VAPB_1_SEL 120
  104. #define CLKID_VAPB_1 122
  105. #define CLKID_VAPB_SEL 123
  106. #define CLKID_VAPB 124
  107. #define CLKID_HDMI_PLL 128
  108. #define CLKID_VID_PLL 129
  109. #define CLKID_VCLK 138
  110. #define CLKID_VCLK2 139
  111. #define CLKID_VCLK_DIV1 148
  112. #define CLKID_VCLK_DIV2 149
  113. #define CLKID_VCLK_DIV4 150
  114. #define CLKID_VCLK_DIV6 151
  115. #define CLKID_VCLK_DIV12 152
  116. #define CLKID_VCLK2_DIV1 153
  117. #define CLKID_VCLK2_DIV2 154
  118. #define CLKID_VCLK2_DIV4 155
  119. #define CLKID_VCLK2_DIV6 156
  120. #define CLKID_VCLK2_DIV12 157
  121. #define CLKID_CTS_ENCI 162
  122. #define CLKID_CTS_ENCP 163
  123. #define CLKID_CTS_VDAC 164
  124. #define CLKID_HDMI_TX 165
  125. #define CLKID_HDMI 168
  126. #define CLKID_MALI_0_SEL 169
  127. #define CLKID_MALI_0 171
  128. #define CLKID_MALI_1_SEL 172
  129. #define CLKID_MALI_1 174
  130. #define CLKID_MALI 175
  131. #define CLKID_MPLL_50M 177
  132. #define CLKID_CPU_CLK 187
  133. #define CLKID_PCIE_PLL 201
  134. #define CLKID_VDEC_1 204
  135. #define CLKID_VDEC_HEVC 207
  136. #define CLKID_VDEC_HEVCF 210
  137. #define CLKID_TS 212
  138. #define CLKID_CPUB_CLK 224
  139. #define CLKID_GP1_PLL 243
  140. #define CLKID_DSU_CLK 252
  141. #define CLKID_CPU1_CLK 253
  142. #define CLKID_CPU2_CLK 254
  143. #define CLKID_CPU3_CLK 255
  144. #define CLKID_SPICC0_SCLK 258
  145. #define CLKID_SPICC1_SCLK 261
  146. #define CLKID_NNA_AXI_CLK 264
  147. #define CLKID_NNA_CORE_CLK 267
  148. #endif /* __G12A_CLKC_H */