exynos7420-clk.h 5.2 KB

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  1. /*
  2. * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  3. * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
  10. #define _DT_BINDINGS_CLOCK_EXYNOS7_H
  11. /* TOPC */
  12. #define DOUT_ACLK_PERIS 1
  13. #define DOUT_SCLK_BUS0_PLL 2
  14. #define DOUT_SCLK_BUS1_PLL 3
  15. #define DOUT_SCLK_CC_PLL 4
  16. #define DOUT_SCLK_MFC_PLL 5
  17. #define DOUT_ACLK_CCORE_133 6
  18. #define DOUT_ACLK_MSCL_532 7
  19. #define ACLK_MSCL_532 8
  20. #define DOUT_SCLK_AUD_PLL 9
  21. #define FOUT_AUD_PLL 10
  22. #define SCLK_AUD_PLL 11
  23. #define SCLK_MFC_PLL_B 12
  24. #define SCLK_MFC_PLL_A 13
  25. #define SCLK_BUS1_PLL_B 14
  26. #define SCLK_BUS1_PLL_A 15
  27. #define SCLK_BUS0_PLL_B 16
  28. #define SCLK_BUS0_PLL_A 17
  29. #define SCLK_CC_PLL_B 18
  30. #define SCLK_CC_PLL_A 19
  31. #define ACLK_CCORE_133 20
  32. #define ACLK_PERIS_66 21
  33. #define TOPC_NR_CLK 22
  34. /* TOP0 */
  35. #define DOUT_ACLK_PERIC1 1
  36. #define DOUT_ACLK_PERIC0 2
  37. #define CLK_SCLK_UART0 3
  38. #define CLK_SCLK_UART1 4
  39. #define CLK_SCLK_UART2 5
  40. #define CLK_SCLK_UART3 6
  41. #define CLK_SCLK_SPI0 7
  42. #define CLK_SCLK_SPI1 8
  43. #define CLK_SCLK_SPI2 9
  44. #define CLK_SCLK_SPI3 10
  45. #define CLK_SCLK_SPI4 11
  46. #define CLK_SCLK_SPDIF 12
  47. #define CLK_SCLK_PCM1 13
  48. #define CLK_SCLK_I2S1 14
  49. #define CLK_ACLK_PERIC0_66 15
  50. #define CLK_ACLK_PERIC1_66 16
  51. #define TOP0_NR_CLK 17
  52. /* TOP1 */
  53. #define DOUT_ACLK_FSYS1_200 1
  54. #define DOUT_ACLK_FSYS0_200 2
  55. #define DOUT_SCLK_MMC2 3
  56. #define DOUT_SCLK_MMC1 4
  57. #define DOUT_SCLK_MMC0 5
  58. #define CLK_SCLK_MMC2 6
  59. #define CLK_SCLK_MMC1 7
  60. #define CLK_SCLK_MMC0 8
  61. #define CLK_ACLK_FSYS0_200 9
  62. #define CLK_ACLK_FSYS1_200 10
  63. #define CLK_SCLK_PHY_FSYS1 11
  64. #define CLK_SCLK_PHY_FSYS1_26M 12
  65. #define MOUT_SCLK_UFSUNIPRO20 13
  66. #define DOUT_SCLK_UFSUNIPRO20 14
  67. #define CLK_SCLK_UFSUNIPRO20 15
  68. #define DOUT_SCLK_PHY_FSYS1 16
  69. #define DOUT_SCLK_PHY_FSYS1_26M 17
  70. #define TOP1_NR_CLK 18
  71. /* CCORE */
  72. #define PCLK_RTC 1
  73. #define CCORE_NR_CLK 2
  74. /* PERIC0 */
  75. #define PCLK_UART0 1
  76. #define SCLK_UART0 2
  77. #define PCLK_HSI2C0 3
  78. #define PCLK_HSI2C1 4
  79. #define PCLK_HSI2C4 5
  80. #define PCLK_HSI2C5 6
  81. #define PCLK_HSI2C9 7
  82. #define PCLK_HSI2C10 8
  83. #define PCLK_HSI2C11 9
  84. #define PCLK_PWM 10
  85. #define SCLK_PWM 11
  86. #define PCLK_ADCIF 12
  87. #define PERIC0_NR_CLK 13
  88. /* PERIC1 */
  89. #define PCLK_UART1 1
  90. #define PCLK_UART2 2
  91. #define PCLK_UART3 3
  92. #define SCLK_UART1 4
  93. #define SCLK_UART2 5
  94. #define SCLK_UART3 6
  95. #define PCLK_HSI2C2 7
  96. #define PCLK_HSI2C3 8
  97. #define PCLK_HSI2C6 9
  98. #define PCLK_HSI2C7 10
  99. #define PCLK_HSI2C8 11
  100. #define PCLK_SPI0 12
  101. #define PCLK_SPI1 13
  102. #define PCLK_SPI2 14
  103. #define PCLK_SPI3 15
  104. #define PCLK_SPI4 16
  105. #define SCLK_SPI0 17
  106. #define SCLK_SPI1 18
  107. #define SCLK_SPI2 19
  108. #define SCLK_SPI3 20
  109. #define SCLK_SPI4 21
  110. #define PCLK_I2S1 22
  111. #define PCLK_PCM1 23
  112. #define PCLK_SPDIF 24
  113. #define SCLK_I2S1 25
  114. #define SCLK_PCM1 26
  115. #define SCLK_SPDIF 27
  116. #define PERIC1_NR_CLK 28
  117. /* PERIS */
  118. #define PCLK_CHIPID 1
  119. #define SCLK_CHIPID 2
  120. #define PCLK_WDT 3
  121. #define PCLK_TMU 4
  122. #define SCLK_TMU 5
  123. #define PERIS_NR_CLK 6
  124. /* FSYS0 */
  125. #define ACLK_MMC2 1
  126. #define ACLK_AXIUS_USBDRD30X_FSYS0X 2
  127. #define ACLK_USBDRD300 3
  128. #define SCLK_USBDRD300_SUSPENDCLK 4
  129. #define SCLK_USBDRD300_REFCLK 5
  130. #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
  131. #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
  132. #define OSCCLK_PHY_CLKOUT_USB30_PHY 8
  133. #define ACLK_PDMA0 9
  134. #define ACLK_PDMA1 10
  135. #define FSYS0_NR_CLK 11
  136. /* FSYS1 */
  137. #define ACLK_MMC1 1
  138. #define ACLK_MMC0 2
  139. #define PHYCLK_UFS20_TX0_SYMBOL 3
  140. #define PHYCLK_UFS20_RX0_SYMBOL 4
  141. #define PHYCLK_UFS20_RX1_SYMBOL 5
  142. #define ACLK_UFS20_LINK 6
  143. #define SCLK_UFSUNIPRO20_USER 7
  144. #define PHYCLK_UFS20_RX1_SYMBOL_USER 8
  145. #define PHYCLK_UFS20_RX0_SYMBOL_USER 9
  146. #define PHYCLK_UFS20_TX0_SYMBOL_USER 10
  147. #define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY 11
  148. #define SCLK_COMBO_PHY_EMBEDDED_26M 12
  149. #define DOUT_PCLK_FSYS1 13
  150. #define PCLK_GPIO_FSYS1 14
  151. #define MOUT_FSYS1_PHYCLK_SEL1 15
  152. #define FSYS1_NR_CLK 16
  153. /* MSCL */
  154. #define USERMUX_ACLK_MSCL_532 1
  155. #define DOUT_PCLK_MSCL 2
  156. #define ACLK_MSCL_0 3
  157. #define ACLK_MSCL_1 4
  158. #define ACLK_JPEG 5
  159. #define ACLK_G2D 6
  160. #define ACLK_LH_ASYNC_SI_MSCL_0 7
  161. #define ACLK_LH_ASYNC_SI_MSCL_1 8
  162. #define ACLK_AXI2ACEL_BRIDGE 9
  163. #define ACLK_XIU_MSCLX_0 10
  164. #define ACLK_XIU_MSCLX_1 11
  165. #define ACLK_QE_MSCL_0 12
  166. #define ACLK_QE_MSCL_1 13
  167. #define ACLK_QE_JPEG 14
  168. #define ACLK_QE_G2D 15
  169. #define ACLK_PPMU_MSCL_0 16
  170. #define ACLK_PPMU_MSCL_1 17
  171. #define ACLK_MSCLNP_133 18
  172. #define ACLK_AHB2APB_MSCL0P 19
  173. #define ACLK_AHB2APB_MSCL1P 20
  174. #define PCLK_MSCL_0 21
  175. #define PCLK_MSCL_1 22
  176. #define PCLK_JPEG 23
  177. #define PCLK_G2D 24
  178. #define PCLK_QE_MSCL_0 25
  179. #define PCLK_QE_MSCL_1 26
  180. #define PCLK_QE_JPEG 27
  181. #define PCLK_QE_G2D 28
  182. #define PCLK_PPMU_MSCL_0 29
  183. #define PCLK_PPMU_MSCL_1 30
  184. #define PCLK_AXI2ACEL_BRIDGE 31
  185. #define PCLK_PMU_MSCL 32
  186. #define MSCL_NR_CLK 33
  187. /* AUD */
  188. #define SCLK_I2S 1
  189. #define SCLK_PCM 2
  190. #define PCLK_I2S 3
  191. #define PCLK_PCM 4
  192. #define ACLK_ADMA 5
  193. #define AUD_NR_CLK 6
  194. #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */