actions,s700-cmu.h 2.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118
  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Device Tree binding constants for Actions Semi S700 Clock Management Unit
  4. *
  5. * Copyright (c) 2014 Actions Semi Inc.
  6. * Author: David Liu <liuwei@actions-semi.com>
  7. *
  8. * Author: Pathiban Nallathambi <pn@denx.de>
  9. * Author: Saravanan Sekar <sravanhome@gmail.com>
  10. */
  11. #ifndef __DT_BINDINGS_CLOCK_S700_H
  12. #define __DT_BINDINGS_CLOCK_S700_H
  13. #define CLK_NONE 0
  14. /* pll clocks */
  15. #define CLK_CORE_PLL 1
  16. #define CLK_DEV_PLL 2
  17. #define CLK_DDR_PLL 3
  18. #define CLK_NAND_PLL 4
  19. #define CLK_DISPLAY_PLL 5
  20. #define CLK_TVOUT_PLL 6
  21. #define CLK_CVBS_PLL 7
  22. #define CLK_AUDIO_PLL 8
  23. #define CLK_ETHERNET_PLL 9
  24. /* system clock */
  25. #define CLK_CPU 10
  26. #define CLK_DEV 11
  27. #define CLK_AHB 12
  28. #define CLK_APB 13
  29. #define CLK_DMAC 14
  30. #define CLK_NOC0_CLK_MUX 15
  31. #define CLK_NOC1_CLK_MUX 16
  32. #define CLK_HP_CLK_MUX 17
  33. #define CLK_HP_CLK_DIV 18
  34. #define CLK_NOC1_CLK_DIV 19
  35. #define CLK_NOC0 20
  36. #define CLK_NOC1 21
  37. #define CLK_SENOR_SRC 22
  38. /* peripheral device clock */
  39. #define CLK_GPIO 23
  40. #define CLK_TIMER 24
  41. #define CLK_DSI 25
  42. #define CLK_CSI 26
  43. #define CLK_SI 27
  44. #define CLK_DE 28
  45. #define CLK_HDE 29
  46. #define CLK_VDE 30
  47. #define CLK_VCE 31
  48. #define CLK_NAND 32
  49. #define CLK_SD0 33
  50. #define CLK_SD1 34
  51. #define CLK_SD2 35
  52. #define CLK_UART0 36
  53. #define CLK_UART1 37
  54. #define CLK_UART2 38
  55. #define CLK_UART3 39
  56. #define CLK_UART4 40
  57. #define CLK_UART5 41
  58. #define CLK_UART6 42
  59. #define CLK_PWM0 43
  60. #define CLK_PWM1 44
  61. #define CLK_PWM2 45
  62. #define CLK_PWM3 46
  63. #define CLK_PWM4 47
  64. #define CLK_PWM5 48
  65. #define CLK_GPU3D 49
  66. #define CLK_I2C0 50
  67. #define CLK_I2C1 51
  68. #define CLK_I2C2 52
  69. #define CLK_I2C3 53
  70. #define CLK_SPI0 54
  71. #define CLK_SPI1 55
  72. #define CLK_SPI2 56
  73. #define CLK_SPI3 57
  74. #define CLK_USB3_480MPLL0 58
  75. #define CLK_USB3_480MPHY0 59
  76. #define CLK_USB3_5GPHY 60
  77. #define CLK_USB3_CCE 61
  78. #define CLK_USB3_MAC 62
  79. #define CLK_LCD 63
  80. #define CLK_HDMI_AUDIO 64
  81. #define CLK_I2SRX 65
  82. #define CLK_I2STX 66
  83. #define CLK_SENSOR0 67
  84. #define CLK_SENSOR1 68
  85. #define CLK_HDMI_DEV 69
  86. #define CLK_ETHERNET 70
  87. #define CLK_RMII_REF 71
  88. #define CLK_USB2H0_PLLEN 72
  89. #define CLK_USB2H0_PHY 73
  90. #define CLK_USB2H0_CCE 74
  91. #define CLK_USB2H1_PLLEN 75
  92. #define CLK_USB2H1_PHY 76
  93. #define CLK_USB2H1_CCE 77
  94. #define CLK_TVOUT 78
  95. #define CLK_THERMAL_SENSOR 79
  96. #define CLK_IRC_SWITCH 80
  97. #define CLK_PCM1 81
  98. #define CLK_NR_CLKS (CLK_PCM1 + 1)
  99. #endif /* __DT_BINDINGS_CLOCK_S700_H */