ti_usb_phy.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**
  3. * ti_usb_phy.c - USB3 and USB3 PHY programming for dwc3
  4. *
  5. * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Author: Kishon Vijay Abraham I <kishon@ti.com>
  8. *
  9. * Taken from Linux Kernel v3.16 (drivers/phy/phy-ti-pipe3.c and
  10. * drivers/phy/phy-omap-usb2.c) and ported to uboot.
  11. *
  12. * "commit 56042e : phy: ti-pipe3: Fix suspend/resume and module reload" for
  13. * phy-ti-pipe3.c
  14. *
  15. * "commit eb82a3 : phy: omap-usb2: Balance pm_runtime_enable() on probe failure
  16. * and remove" for phy-omap-usb2.c
  17. */
  18. #include <common.h>
  19. #include <malloc.h>
  20. #include <ti-usb-phy-uboot.h>
  21. #include <dm/device_compat.h>
  22. #include <dm/devres.h>
  23. #include <linux/bitops.h>
  24. #include <linux/delay.h>
  25. #include <linux/ioport.h>
  26. #include <asm/io.h>
  27. #include <asm/arch/sys_proto.h>
  28. #include <dm.h>
  29. #include "linux-compat.h"
  30. #define PLL_STATUS 0x00000004
  31. #define PLL_GO 0x00000008
  32. #define PLL_CONFIGURATION1 0x0000000C
  33. #define PLL_CONFIGURATION2 0x00000010
  34. #define PLL_CONFIGURATION3 0x00000014
  35. #define PLL_CONFIGURATION4 0x00000020
  36. #define PLL_REGM_MASK 0x001FFE00
  37. #define PLL_REGM_SHIFT 0x9
  38. #define PLL_REGM_F_MASK 0x0003FFFF
  39. #define PLL_REGM_F_SHIFT 0x0
  40. #define PLL_REGN_MASK 0x000001FE
  41. #define PLL_REGN_SHIFT 0x1
  42. #define PLL_SELFREQDCO_MASK 0x0000000E
  43. #define PLL_SELFREQDCO_SHIFT 0x1
  44. #define PLL_SD_MASK 0x0003FC00
  45. #define PLL_SD_SHIFT 10
  46. #define SET_PLL_GO 0x1
  47. #define PLL_LDOPWDN BIT(15)
  48. #define PLL_TICOPWDN BIT(16)
  49. #define PLL_LOCK 0x2
  50. #define PLL_IDLE 0x1
  51. #define OMAP_CTRL_DEV_PHY_PD BIT(0)
  52. #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
  53. #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
  54. #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
  55. #define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
  56. #define OMAP_CTRL_USB3_PHY_TX_RX_POWERON 0x3
  57. #define OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF 0x0
  58. #define OMAP_CTRL_USB2_PHY_PD BIT(28)
  59. #define AM437X_CTRL_USB2_PHY_PD BIT(0)
  60. #define AM437X_CTRL_USB2_OTG_PD BIT(1)
  61. #define AM437X_CTRL_USB2_OTGVDET_EN BIT(19)
  62. #define AM437X_CTRL_USB2_OTGSESSEND_EN BIT(20)
  63. static LIST_HEAD(ti_usb_phy_list);
  64. typedef unsigned int u32;
  65. struct usb3_dpll_params {
  66. u16 m;
  67. u8 n;
  68. u8 freq:3;
  69. u8 sd;
  70. u32 mf;
  71. };
  72. struct usb3_dpll_map {
  73. unsigned long rate;
  74. struct usb3_dpll_params params;
  75. struct usb3_dpll_map *dpll_map;
  76. };
  77. struct ti_usb_phy {
  78. void __iomem *pll_ctrl_base;
  79. void __iomem *usb2_phy_power;
  80. void __iomem *usb3_phy_power;
  81. struct usb3_dpll_map *dpll_map;
  82. struct list_head list;
  83. int index;
  84. };
  85. static struct usb3_dpll_map dpll_map_usb[] = {
  86. {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
  87. {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
  88. {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
  89. {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
  90. {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
  91. {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
  92. { }, /* Terminator */
  93. };
  94. static inline unsigned int ti_usb3_readl(void __iomem *base, u32 offset)
  95. {
  96. return readl(base + offset);
  97. }
  98. static inline void ti_usb3_writel(void __iomem *base, u32 offset, u32 value)
  99. {
  100. writel(value, base + offset);
  101. }
  102. #ifndef CONFIG_AM43XX
  103. static struct usb3_dpll_params *ti_usb3_get_dpll_params(struct ti_usb_phy *phy)
  104. {
  105. unsigned long rate;
  106. struct usb3_dpll_map *dpll_map = phy->dpll_map;
  107. rate = get_sys_clk_freq();
  108. for (; dpll_map->rate; dpll_map++) {
  109. if (rate == dpll_map->rate)
  110. return &dpll_map->params;
  111. }
  112. log_err("No DPLL configuration for %lu Hz SYS CLK\n", rate);
  113. return NULL;
  114. }
  115. static int ti_usb3_dpll_wait_lock(struct ti_usb_phy *phy)
  116. {
  117. u32 val;
  118. do {
  119. val = ti_usb3_readl(phy->pll_ctrl_base, PLL_STATUS);
  120. if (val & PLL_LOCK)
  121. break;
  122. } while (1);
  123. return 0;
  124. }
  125. static int ti_usb3_dpll_program(struct ti_usb_phy *phy)
  126. {
  127. u32 val;
  128. struct usb3_dpll_params *dpll_params;
  129. if (!phy->pll_ctrl_base)
  130. return -EINVAL;
  131. dpll_params = ti_usb3_get_dpll_params(phy);
  132. if (!dpll_params)
  133. return -EINVAL;
  134. val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
  135. val &= ~PLL_REGN_MASK;
  136. val |= dpll_params->n << PLL_REGN_SHIFT;
  137. ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
  138. val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  139. val &= ~PLL_SELFREQDCO_MASK;
  140. val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
  141. ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  142. val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
  143. val &= ~PLL_REGM_MASK;
  144. val |= dpll_params->m << PLL_REGM_SHIFT;
  145. ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
  146. val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
  147. val &= ~PLL_REGM_F_MASK;
  148. val |= dpll_params->mf << PLL_REGM_F_SHIFT;
  149. ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
  150. val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
  151. val &= ~PLL_SD_MASK;
  152. val |= dpll_params->sd << PLL_SD_SHIFT;
  153. ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
  154. ti_usb3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
  155. return ti_usb3_dpll_wait_lock(phy);
  156. }
  157. #endif
  158. void ti_usb2_phy_power(struct ti_usb_phy *phy, int on)
  159. {
  160. u32 val;
  161. val = readl(phy->usb2_phy_power);
  162. if (on) {
  163. #if defined(CONFIG_DRA7XX)
  164. if (phy->index == 1)
  165. val &= ~OMAP_CTRL_USB2_PHY_PD;
  166. else
  167. val &= ~OMAP_CTRL_DEV_PHY_PD;
  168. #elif defined(CONFIG_AM43XX)
  169. val &= ~(AM437X_CTRL_USB2_PHY_PD |
  170. AM437X_CTRL_USB2_OTG_PD);
  171. val |= (AM437X_CTRL_USB2_OTGVDET_EN |
  172. AM437X_CTRL_USB2_OTGSESSEND_EN);
  173. #endif
  174. } else {
  175. #if defined(CONFIG_DRA7XX)
  176. if (phy->index == 1)
  177. val |= OMAP_CTRL_USB2_PHY_PD;
  178. else
  179. val |= OMAP_CTRL_DEV_PHY_PD;
  180. #elif defined(CONFIG_AM43XX)
  181. val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
  182. AM437X_CTRL_USB2_OTGSESSEND_EN);
  183. val |= (AM437X_CTRL_USB2_PHY_PD |
  184. AM437X_CTRL_USB2_OTG_PD);
  185. #endif
  186. }
  187. writel(val, phy->usb2_phy_power);
  188. }
  189. #ifndef CONFIG_AM43XX
  190. void ti_usb3_phy_power(struct ti_usb_phy *phy, int on)
  191. {
  192. u32 val;
  193. u32 rate;
  194. rate = get_sys_clk_freq();
  195. rate = rate/1000000;
  196. if (!phy->usb3_phy_power)
  197. return;
  198. val = readl(phy->usb3_phy_power);
  199. if (on) {
  200. val &= ~(OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK |
  201. OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_MASK);
  202. val |= (OMAP_CTRL_USB3_PHY_TX_RX_POWERON) <<
  203. OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT;
  204. val |= rate <<
  205. OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_SHIFT;
  206. } else {
  207. val &= ~OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK;
  208. val |= OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF <<
  209. OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT;
  210. }
  211. writel(val, phy->usb3_phy_power);
  212. }
  213. #endif
  214. /**
  215. * ti_usb_phy_uboot_init - usb phy uboot initialization code
  216. * @dev: struct ti_usb_phy_device containing initialization data
  217. *
  218. * Entry point for ti usb phy driver. This driver handles initialization
  219. * of both usb2 phy and usb3 phy. Pointer to ti_usb_phy_device should be
  220. * passed containing base address and other initialization data.
  221. * Returns '0' on success and a negative value on failure.
  222. *
  223. * Generally called from board_usb_init() implemented in board file.
  224. */
  225. int ti_usb_phy_uboot_init(struct ti_usb_phy_device *dev)
  226. {
  227. struct ti_usb_phy *phy;
  228. phy = devm_kzalloc(NULL, sizeof(*phy), GFP_KERNEL);
  229. if (!phy) {
  230. log_err("unable to alloc mem for TI USB3 PHY\n");
  231. return -ENOMEM;
  232. }
  233. phy->dpll_map = dpll_map_usb;
  234. phy->index = dev->index;
  235. phy->pll_ctrl_base = dev->pll_ctrl_base;
  236. phy->usb2_phy_power = dev->usb2_phy_power;
  237. phy->usb3_phy_power = dev->usb3_phy_power;
  238. #ifndef CONFIG_AM43XX
  239. ti_usb3_dpll_program(phy);
  240. ti_usb3_phy_power(phy, 1);
  241. #endif
  242. ti_usb2_phy_power(phy, 1);
  243. mdelay(150);
  244. list_add_tail(&phy->list, &ti_usb_phy_list);
  245. return 0;
  246. }
  247. /**
  248. * ti_usb_phy_uboot_exit - usb phy uboot cleanup code
  249. * @index: index of this controller
  250. *
  251. * Performs cleanup of memory allocated in ti_usb_phy_uboot_init.
  252. * index of _this_ controller should be passed and should match with
  253. * the index passed in ti_usb_phy_device during init.
  254. *
  255. * Generally called from board file.
  256. */
  257. void ti_usb_phy_uboot_exit(int index)
  258. {
  259. struct ti_usb_phy *phy = NULL;
  260. list_for_each_entry(phy, &ti_usb_phy_list, list) {
  261. if (phy->index != index)
  262. continue;
  263. ti_usb2_phy_power(phy, 0);
  264. #ifndef CONFIG_AM43XX
  265. ti_usb3_phy_power(phy, 0);
  266. #endif
  267. list_del(&phy->list);
  268. kfree(phy);
  269. break;
  270. }
  271. }