samsung_usb_phy.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * samsung_usb_phy.c - DesignWare USB3 (DWC3) PHY handling file
  4. *
  5. * Copyright (C) 2015 Samsung Electronics
  6. *
  7. * Author: Joonyoung Shim <jy0922.shim@samsung.com>
  8. */
  9. #include <common.h>
  10. #include <asm/arch/power.h>
  11. #include <asm/arch/xhci-exynos.h>
  12. #include <linux/delay.h>
  13. void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
  14. {
  15. u32 reg;
  16. /* Reset USB 3.0 PHY */
  17. writel(0x0, &phy->phy_reg0);
  18. clrbits_le32(&phy->phy_param0,
  19. /* Select PHY CLK source */
  20. PHYPARAM0_REF_USE_PAD |
  21. /* Set Loss-of-Signal Detector sensitivity */
  22. PHYPARAM0_REF_LOSLEVEL_MASK);
  23. setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
  24. writel(0x0, &phy->phy_resume);
  25. /*
  26. * Setting the Frame length Adj value[6:1] to default 0x20
  27. * See xHCI 1.0 spec, 5.2.4
  28. */
  29. setbits_le32(&phy->link_system,
  30. LINKSYSTEM_XHCI_VERSION_CONTROL |
  31. LINKSYSTEM_FLADJ(0x20));
  32. /* Set Tx De-Emphasis level */
  33. clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
  34. setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
  35. setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
  36. /* PHYTEST POWERDOWN Control */
  37. clrbits_le32(&phy->phy_test,
  38. PHYTEST_POWERDOWN_SSP |
  39. PHYTEST_POWERDOWN_HSP);
  40. /* UTMI Power Control */
  41. writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
  42. /* Use core clock from main PLL */
  43. reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
  44. /* Default 24Mhz crystal clock */
  45. PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
  46. PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
  47. PHYCLKRST_SSC_REFCLKSEL(0) |
  48. /* Force PortReset of PHY */
  49. PHYCLKRST_PORTRESET |
  50. /* Digital power supply in normal operating mode */
  51. PHYCLKRST_RETENABLEN |
  52. /* Enable ref clock for SS function */
  53. PHYCLKRST_REF_SSP_EN |
  54. /* Enable spread spectrum */
  55. PHYCLKRST_SSC_EN |
  56. /* Power down HS Bias and PLL blocks in suspend mode */
  57. PHYCLKRST_COMMONONN;
  58. writel(reg, &phy->phy_clk_rst);
  59. /* giving time to Phy clock to settle before resetting */
  60. udelay(10);
  61. reg &= ~PHYCLKRST_PORTRESET;
  62. writel(reg, &phy->phy_clk_rst);
  63. }