io.h 1.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /**
  3. * io.h - DesignWare USB3 DRD IO Header
  4. *
  5. * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. *
  10. * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/io.h) and ported
  11. * to uboot.
  12. *
  13. * commit 2c4cbe6e5a : usb: dwc3: add tracepoints to aid debugging
  14. *
  15. */
  16. #ifndef __DRIVERS_USB_DWC3_IO_H
  17. #define __DRIVERS_USB_DWC3_IO_H
  18. #include <cpu_func.h>
  19. #include <asm/io.h>
  20. #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
  21. static inline u32 dwc3_readl(void __iomem *base, u32 offset)
  22. {
  23. unsigned long offs = offset - DWC3_GLOBALS_REGS_START;
  24. u32 value;
  25. /*
  26. * We requested the mem region starting from the Globals address
  27. * space, see dwc3_probe in core.c.
  28. * However, the offsets are given starting from xHCI address space.
  29. */
  30. value = readl(base + offs);
  31. return value;
  32. }
  33. static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
  34. {
  35. unsigned long offs = offset - DWC3_GLOBALS_REGS_START;
  36. /*
  37. * We requested the mem region starting from the Globals address
  38. * space, see dwc3_probe in core.c.
  39. * However, the offsets are given starting from xHCI address space.
  40. */
  41. writel(value, base + offs);
  42. }
  43. static inline void dwc3_flush_cache(uintptr_t addr, int length)
  44. {
  45. flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
  46. }
  47. #endif /* __DRIVERS_USB_DWC3_IO_H */