gadget.c 64 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
  4. *
  5. * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. *
  10. * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
  11. * to uboot.
  12. *
  13. * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
  14. */
  15. #include <common.h>
  16. #include <cpu_func.h>
  17. #include <log.h>
  18. #include <malloc.h>
  19. #include <dm.h>
  20. #include <dm/device_compat.h>
  21. #include <dm/devres.h>
  22. #include <linux/bug.h>
  23. #include <linux/delay.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/list.h>
  26. #include <linux/usb/ch9.h>
  27. #include <linux/usb/gadget.h>
  28. #include "core.h"
  29. #include "gadget.h"
  30. #include "io.h"
  31. #include "linux-compat.h"
  32. /**
  33. * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  34. * @dwc: pointer to our context structure
  35. * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  36. *
  37. * Caller should take care of locking. This function will
  38. * return 0 on success or -EINVAL if wrong Test Selector
  39. * is passed
  40. */
  41. int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  42. {
  43. u32 reg;
  44. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  45. reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  46. switch (mode) {
  47. case TEST_J:
  48. case TEST_K:
  49. case TEST_SE0_NAK:
  50. case TEST_PACKET:
  51. case TEST_FORCE_EN:
  52. reg |= mode << 1;
  53. break;
  54. default:
  55. return -EINVAL;
  56. }
  57. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  58. return 0;
  59. }
  60. /**
  61. * dwc3_gadget_get_link_state - Gets current state of USB Link
  62. * @dwc: pointer to our context structure
  63. *
  64. * Caller should take care of locking. This function will
  65. * return the link state on success (>= 0) or -ETIMEDOUT.
  66. */
  67. int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  68. {
  69. u32 reg;
  70. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  71. return DWC3_DSTS_USBLNKST(reg);
  72. }
  73. /**
  74. * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  75. * @dwc: pointer to our context structure
  76. * @state: the state to put link into
  77. *
  78. * Caller should take care of locking. This function will
  79. * return 0 on success or -ETIMEDOUT.
  80. */
  81. int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  82. {
  83. int retries = 10000;
  84. u32 reg;
  85. /*
  86. * Wait until device controller is ready. Only applies to 1.94a and
  87. * later RTL.
  88. */
  89. if (dwc->revision >= DWC3_REVISION_194A) {
  90. while (--retries) {
  91. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  92. if (reg & DWC3_DSTS_DCNRD)
  93. udelay(5);
  94. else
  95. break;
  96. }
  97. if (retries <= 0)
  98. return -ETIMEDOUT;
  99. }
  100. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  101. reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
  102. /* set requested state */
  103. reg |= DWC3_DCTL_ULSTCHNGREQ(state);
  104. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  105. /*
  106. * The following code is racy when called from dwc3_gadget_wakeup,
  107. * and is not needed, at least on newer versions
  108. */
  109. if (dwc->revision >= DWC3_REVISION_194A)
  110. return 0;
  111. /* wait for a change in DSTS */
  112. retries = 10000;
  113. while (--retries) {
  114. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  115. if (DWC3_DSTS_USBLNKST(reg) == state)
  116. return 0;
  117. udelay(5);
  118. }
  119. dev_vdbg(dwc->dev, "link state change request timed out\n");
  120. return -ETIMEDOUT;
  121. }
  122. /**
  123. * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
  124. * @dwc: pointer to our context structure
  125. *
  126. * This function will a best effort FIFO allocation in order
  127. * to improve FIFO usage and throughput, while still allowing
  128. * us to enable as many endpoints as possible.
  129. *
  130. * Keep in mind that this operation will be highly dependent
  131. * on the configured size for RAM1 - which contains TxFifo -,
  132. * the amount of endpoints enabled on coreConsultant tool, and
  133. * the width of the Master Bus.
  134. *
  135. * In the ideal world, we would always be able to satisfy the
  136. * following equation:
  137. *
  138. * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
  139. * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
  140. *
  141. * Unfortunately, due to many variables that's not always the case.
  142. */
  143. int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
  144. {
  145. int last_fifo_depth = 0;
  146. int fifo_size;
  147. int mdwidth;
  148. int num;
  149. if (!dwc->needs_fifo_resize)
  150. return 0;
  151. mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
  152. /* MDWIDTH is represented in bits, we need it in bytes */
  153. mdwidth >>= 3;
  154. /*
  155. * FIXME For now we will only allocate 1 wMaxPacketSize space
  156. * for each enabled endpoint, later patches will come to
  157. * improve this algorithm so that we better use the internal
  158. * FIFO space
  159. */
  160. for (num = 0; num < dwc->num_in_eps; num++) {
  161. /* bit0 indicates direction; 1 means IN ep */
  162. struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
  163. int mult = 1;
  164. int tmp;
  165. if (!(dep->flags & DWC3_EP_ENABLED))
  166. continue;
  167. if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
  168. || usb_endpoint_xfer_isoc(dep->endpoint.desc))
  169. mult = 3;
  170. /*
  171. * REVISIT: the following assumes we will always have enough
  172. * space available on the FIFO RAM for all possible use cases.
  173. * Make sure that's true somehow and change FIFO allocation
  174. * accordingly.
  175. *
  176. * If we have Bulk or Isochronous endpoints, we want
  177. * them to be able to be very, very fast. So we're giving
  178. * those endpoints a fifo_size which is enough for 3 full
  179. * packets
  180. */
  181. tmp = mult * (dep->endpoint.maxpacket + mdwidth);
  182. tmp += mdwidth;
  183. fifo_size = DIV_ROUND_UP(tmp, mdwidth);
  184. fifo_size |= (last_fifo_depth << 16);
  185. dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
  186. dep->name, last_fifo_depth, fifo_size & 0xffff);
  187. dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
  188. last_fifo_depth += (fifo_size & 0xffff);
  189. }
  190. return 0;
  191. }
  192. void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
  193. int status)
  194. {
  195. struct dwc3 *dwc = dep->dwc;
  196. if (req->queued) {
  197. dep->busy_slot++;
  198. /*
  199. * Skip LINK TRB. We can't use req->trb and check for
  200. * DWC3_TRBCTL_LINK_TRB because it points the TRB we
  201. * just completed (not the LINK TRB).
  202. */
  203. if (((dep->busy_slot & DWC3_TRB_MASK) ==
  204. DWC3_TRB_NUM- 1) &&
  205. usb_endpoint_xfer_isoc(dep->endpoint.desc))
  206. dep->busy_slot++;
  207. req->queued = false;
  208. }
  209. list_del(&req->list);
  210. req->trb = NULL;
  211. if (req->request.length)
  212. dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length);
  213. if (req->request.status == -EINPROGRESS)
  214. req->request.status = status;
  215. if (dwc->ep0_bounced && dep->number == 0)
  216. dwc->ep0_bounced = false;
  217. else
  218. usb_gadget_unmap_request(&dwc->gadget, &req->request,
  219. req->direction);
  220. dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
  221. req, dep->name, req->request.actual,
  222. req->request.length, status);
  223. spin_unlock(&dwc->lock);
  224. usb_gadget_giveback_request(&dep->endpoint, &req->request);
  225. spin_lock(&dwc->lock);
  226. }
  227. int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
  228. {
  229. u32 timeout = 500;
  230. u32 reg;
  231. dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
  232. dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
  233. do {
  234. reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
  235. if (!(reg & DWC3_DGCMD_CMDACT)) {
  236. dev_vdbg(dwc->dev, "Command Complete --> %d\n",
  237. DWC3_DGCMD_STATUS(reg));
  238. return 0;
  239. }
  240. /*
  241. * We can't sleep here, because it's also called from
  242. * interrupt context.
  243. */
  244. timeout--;
  245. if (!timeout)
  246. return -ETIMEDOUT;
  247. udelay(1);
  248. } while (1);
  249. }
  250. int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
  251. unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
  252. {
  253. u32 timeout = 500;
  254. u32 reg;
  255. dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
  256. dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
  257. dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
  258. dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
  259. do {
  260. reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
  261. if (!(reg & DWC3_DEPCMD_CMDACT)) {
  262. dev_vdbg(dwc->dev, "Command Complete --> %d\n",
  263. DWC3_DEPCMD_STATUS(reg));
  264. return 0;
  265. }
  266. /*
  267. * We can't sleep here, because it is also called from
  268. * interrupt context.
  269. */
  270. timeout--;
  271. if (!timeout)
  272. return -ETIMEDOUT;
  273. udelay(1);
  274. } while (1);
  275. }
  276. static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
  277. struct dwc3_trb *trb)
  278. {
  279. u32 offset = (char *) trb - (char *) dep->trb_pool;
  280. return dep->trb_pool_dma + offset;
  281. }
  282. static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
  283. {
  284. if (dep->trb_pool)
  285. return 0;
  286. if (dep->number == 0 || dep->number == 1)
  287. return 0;
  288. dep->trb_pool = dma_alloc_coherent(sizeof(struct dwc3_trb) *
  289. DWC3_TRB_NUM,
  290. (unsigned long *)&dep->trb_pool_dma);
  291. if (!dep->trb_pool) {
  292. dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
  293. dep->name);
  294. return -ENOMEM;
  295. }
  296. return 0;
  297. }
  298. static void dwc3_free_trb_pool(struct dwc3_ep *dep)
  299. {
  300. dma_free_coherent(dep->trb_pool);
  301. dep->trb_pool = NULL;
  302. dep->trb_pool_dma = 0;
  303. }
  304. static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
  305. {
  306. struct dwc3_gadget_ep_cmd_params params;
  307. u32 cmd;
  308. memset(&params, 0x00, sizeof(params));
  309. if (dep->number != 1) {
  310. cmd = DWC3_DEPCMD_DEPSTARTCFG;
  311. /* XferRscIdx == 0 for ep0 and 2 for the remaining */
  312. if (dep->number > 1) {
  313. if (dwc->start_config_issued)
  314. return 0;
  315. dwc->start_config_issued = true;
  316. cmd |= DWC3_DEPCMD_PARAM(2);
  317. }
  318. return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
  319. }
  320. return 0;
  321. }
  322. static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
  323. const struct usb_endpoint_descriptor *desc,
  324. const struct usb_ss_ep_comp_descriptor *comp_desc,
  325. bool ignore, bool restore)
  326. {
  327. struct dwc3_gadget_ep_cmd_params params;
  328. memset(&params, 0x00, sizeof(params));
  329. params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
  330. | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
  331. /* Burst size is only needed in SuperSpeed mode */
  332. if (dwc->gadget.speed == USB_SPEED_SUPER) {
  333. u32 burst = dep->endpoint.maxburst - 1;
  334. params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
  335. }
  336. if (ignore)
  337. params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
  338. if (restore) {
  339. params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
  340. params.param2 |= dep->saved_state;
  341. }
  342. params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
  343. | DWC3_DEPCFG_XFER_NOT_READY_EN;
  344. if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
  345. params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
  346. | DWC3_DEPCFG_STREAM_EVENT_EN;
  347. dep->stream_capable = true;
  348. }
  349. if (!usb_endpoint_xfer_control(desc))
  350. params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
  351. /*
  352. * We are doing 1:1 mapping for endpoints, meaning
  353. * Physical Endpoints 2 maps to Logical Endpoint 2 and
  354. * so on. We consider the direction bit as part of the physical
  355. * endpoint number. So USB endpoint 0x81 is 0x03.
  356. */
  357. params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
  358. /*
  359. * We must use the lower 16 TX FIFOs even though
  360. * HW might have more
  361. */
  362. if (dep->direction)
  363. params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
  364. if (desc->bInterval) {
  365. params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
  366. dep->interval = 1 << (desc->bInterval - 1);
  367. }
  368. return dwc3_send_gadget_ep_cmd(dwc, dep->number,
  369. DWC3_DEPCMD_SETEPCONFIG, &params);
  370. }
  371. static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
  372. {
  373. struct dwc3_gadget_ep_cmd_params params;
  374. memset(&params, 0x00, sizeof(params));
  375. params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
  376. return dwc3_send_gadget_ep_cmd(dwc, dep->number,
  377. DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
  378. }
  379. /**
  380. * __dwc3_gadget_ep_enable - Initializes a HW endpoint
  381. * @dep: endpoint to be initialized
  382. * @desc: USB Endpoint Descriptor
  383. *
  384. * Caller should take care of locking
  385. */
  386. static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
  387. const struct usb_endpoint_descriptor *desc,
  388. const struct usb_ss_ep_comp_descriptor *comp_desc,
  389. bool ignore, bool restore)
  390. {
  391. struct dwc3 *dwc = dep->dwc;
  392. u32 reg;
  393. int ret;
  394. dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
  395. if (!(dep->flags & DWC3_EP_ENABLED)) {
  396. ret = dwc3_gadget_start_config(dwc, dep);
  397. if (ret)
  398. return ret;
  399. }
  400. ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
  401. restore);
  402. if (ret)
  403. return ret;
  404. if (!(dep->flags & DWC3_EP_ENABLED)) {
  405. struct dwc3_trb *trb_st_hw;
  406. struct dwc3_trb *trb_link;
  407. ret = dwc3_gadget_set_xfer_resource(dwc, dep);
  408. if (ret)
  409. return ret;
  410. dep->endpoint.desc = desc;
  411. dep->comp_desc = comp_desc;
  412. dep->type = usb_endpoint_type(desc);
  413. dep->flags |= DWC3_EP_ENABLED;
  414. reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
  415. reg |= DWC3_DALEPENA_EP(dep->number);
  416. dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
  417. if (!usb_endpoint_xfer_isoc(desc))
  418. return 0;
  419. /* Link TRB for ISOC. The HWO bit is never reset */
  420. trb_st_hw = &dep->trb_pool[0];
  421. trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
  422. memset(trb_link, 0, sizeof(*trb_link));
  423. trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
  424. trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
  425. trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
  426. trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
  427. }
  428. return 0;
  429. }
  430. static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
  431. static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
  432. {
  433. struct dwc3_request *req;
  434. if (!list_empty(&dep->req_queued)) {
  435. dwc3_stop_active_transfer(dwc, dep->number, true);
  436. /* - giveback all requests to gadget driver */
  437. while (!list_empty(&dep->req_queued)) {
  438. req = next_request(&dep->req_queued);
  439. dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
  440. }
  441. }
  442. while (!list_empty(&dep->request_list)) {
  443. req = next_request(&dep->request_list);
  444. dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
  445. }
  446. }
  447. /**
  448. * __dwc3_gadget_ep_disable - Disables a HW endpoint
  449. * @dep: the endpoint to disable
  450. *
  451. * This function also removes requests which are currently processed ny the
  452. * hardware and those which are not yet scheduled.
  453. * Caller should take care of locking.
  454. */
  455. static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
  456. {
  457. struct dwc3 *dwc = dep->dwc;
  458. u32 reg;
  459. dwc3_remove_requests(dwc, dep);
  460. /* make sure HW endpoint isn't stalled */
  461. if (dep->flags & DWC3_EP_STALL)
  462. __dwc3_gadget_ep_set_halt(dep, 0, false);
  463. reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
  464. reg &= ~DWC3_DALEPENA_EP(dep->number);
  465. dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
  466. dep->stream_capable = false;
  467. dep->endpoint.desc = NULL;
  468. dep->comp_desc = NULL;
  469. dep->type = 0;
  470. dep->flags = 0;
  471. return 0;
  472. }
  473. /* -------------------------------------------------------------------------- */
  474. static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
  475. const struct usb_endpoint_descriptor *desc)
  476. {
  477. return -EINVAL;
  478. }
  479. static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
  480. {
  481. return -EINVAL;
  482. }
  483. /* -------------------------------------------------------------------------- */
  484. static int dwc3_gadget_ep_enable(struct usb_ep *ep,
  485. const struct usb_endpoint_descriptor *desc)
  486. {
  487. struct dwc3_ep *dep;
  488. unsigned long flags;
  489. int ret;
  490. if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
  491. pr_debug("dwc3: invalid parameters\n");
  492. return -EINVAL;
  493. }
  494. if (!desc->wMaxPacketSize) {
  495. pr_debug("dwc3: missing wMaxPacketSize\n");
  496. return -EINVAL;
  497. }
  498. dep = to_dwc3_ep(ep);
  499. if (dep->flags & DWC3_EP_ENABLED) {
  500. WARN(true, "%s is already enabled\n",
  501. dep->name);
  502. return 0;
  503. }
  504. switch (usb_endpoint_type(desc)) {
  505. case USB_ENDPOINT_XFER_CONTROL:
  506. strlcat(dep->name, "-control", sizeof(dep->name));
  507. break;
  508. case USB_ENDPOINT_XFER_ISOC:
  509. strlcat(dep->name, "-isoc", sizeof(dep->name));
  510. break;
  511. case USB_ENDPOINT_XFER_BULK:
  512. strlcat(dep->name, "-bulk", sizeof(dep->name));
  513. break;
  514. case USB_ENDPOINT_XFER_INT:
  515. strlcat(dep->name, "-int", sizeof(dep->name));
  516. break;
  517. default:
  518. dev_err(dep->dwc->dev, "invalid endpoint transfer type\n");
  519. }
  520. spin_lock_irqsave(&dwc->lock, flags);
  521. ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
  522. spin_unlock_irqrestore(&dwc->lock, flags);
  523. return ret;
  524. }
  525. static int dwc3_gadget_ep_disable(struct usb_ep *ep)
  526. {
  527. struct dwc3_ep *dep;
  528. unsigned long flags;
  529. int ret;
  530. if (!ep) {
  531. pr_debug("dwc3: invalid parameters\n");
  532. return -EINVAL;
  533. }
  534. dep = to_dwc3_ep(ep);
  535. if (!(dep->flags & DWC3_EP_ENABLED)) {
  536. WARN(true, "%s is already disabled\n",
  537. dep->name);
  538. return 0;
  539. }
  540. snprintf(dep->name, sizeof(dep->name), "ep%d%s",
  541. dep->number >> 1,
  542. (dep->number & 1) ? "in" : "out");
  543. spin_lock_irqsave(&dwc->lock, flags);
  544. ret = __dwc3_gadget_ep_disable(dep);
  545. spin_unlock_irqrestore(&dwc->lock, flags);
  546. return ret;
  547. }
  548. static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
  549. gfp_t gfp_flags)
  550. {
  551. struct dwc3_request *req;
  552. struct dwc3_ep *dep = to_dwc3_ep(ep);
  553. req = kzalloc(sizeof(*req), gfp_flags);
  554. if (!req)
  555. return NULL;
  556. req->epnum = dep->number;
  557. req->dep = dep;
  558. return &req->request;
  559. }
  560. static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
  561. struct usb_request *request)
  562. {
  563. struct dwc3_request *req = to_dwc3_request(request);
  564. kfree(req);
  565. }
  566. /**
  567. * dwc3_prepare_one_trb - setup one TRB from one request
  568. * @dep: endpoint for which this request is prepared
  569. * @req: dwc3_request pointer
  570. */
  571. static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
  572. struct dwc3_request *req, dma_addr_t dma,
  573. unsigned length, unsigned last, unsigned chain, unsigned node)
  574. {
  575. struct dwc3_trb *trb;
  576. dev_vdbg(dep->dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
  577. dep->name, req, (unsigned long long)dma,
  578. length, last ? " last" : "", chain ? " chain" : "");
  579. trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
  580. if (!req->trb) {
  581. dwc3_gadget_move_request_queued(req);
  582. req->trb = trb;
  583. req->trb_dma = dwc3_trb_dma_offset(dep, trb);
  584. req->start_slot = dep->free_slot & DWC3_TRB_MASK;
  585. }
  586. dep->free_slot++;
  587. /* Skip the LINK-TRB on ISOC */
  588. if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
  589. usb_endpoint_xfer_isoc(dep->endpoint.desc))
  590. dep->free_slot++;
  591. trb->size = DWC3_TRB_SIZE_LENGTH(length);
  592. trb->bpl = lower_32_bits(dma);
  593. trb->bph = upper_32_bits(dma);
  594. switch (usb_endpoint_type(dep->endpoint.desc)) {
  595. case USB_ENDPOINT_XFER_CONTROL:
  596. trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
  597. break;
  598. case USB_ENDPOINT_XFER_ISOC:
  599. if (!node)
  600. trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
  601. else
  602. trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
  603. break;
  604. case USB_ENDPOINT_XFER_BULK:
  605. case USB_ENDPOINT_XFER_INT:
  606. trb->ctrl = DWC3_TRBCTL_NORMAL;
  607. break;
  608. default:
  609. /*
  610. * This is only possible with faulty memory because we
  611. * checked it already :)
  612. */
  613. BUG();
  614. }
  615. if (!req->request.no_interrupt && !chain)
  616. trb->ctrl |= DWC3_TRB_CTRL_IOC;
  617. if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  618. trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
  619. trb->ctrl |= DWC3_TRB_CTRL_CSP;
  620. } else if (last) {
  621. trb->ctrl |= DWC3_TRB_CTRL_LST;
  622. }
  623. if (chain)
  624. trb->ctrl |= DWC3_TRB_CTRL_CHN;
  625. if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
  626. trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
  627. trb->ctrl |= DWC3_TRB_CTRL_HWO;
  628. dwc3_flush_cache((uintptr_t)dma, length);
  629. dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
  630. }
  631. /*
  632. * dwc3_prepare_trbs - setup TRBs from requests
  633. * @dep: endpoint for which requests are being prepared
  634. * @starting: true if the endpoint is idle and no requests are queued.
  635. *
  636. * The function goes through the requests list and sets up TRBs for the
  637. * transfers. The function returns once there are no more TRBs available or
  638. * it runs out of requests.
  639. */
  640. static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
  641. {
  642. struct dwc3_request *req, *n;
  643. u32 trbs_left;
  644. u32 max;
  645. BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
  646. /* the first request must not be queued */
  647. trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
  648. /* Can't wrap around on a non-isoc EP since there's no link TRB */
  649. if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  650. max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
  651. if (trbs_left > max)
  652. trbs_left = max;
  653. }
  654. /*
  655. * If busy & slot are equal than it is either full or empty. If we are
  656. * starting to process requests then we are empty. Otherwise we are
  657. * full and don't do anything
  658. */
  659. if (!trbs_left) {
  660. if (!starting)
  661. return;
  662. trbs_left = DWC3_TRB_NUM;
  663. /*
  664. * In case we start from scratch, we queue the ISOC requests
  665. * starting from slot 1. This is done because we use ring
  666. * buffer and have no LST bit to stop us. Instead, we place
  667. * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
  668. * after the first request so we start at slot 1 and have
  669. * 7 requests proceed before we hit the first IOC.
  670. * Other transfer types don't use the ring buffer and are
  671. * processed from the first TRB until the last one. Since we
  672. * don't wrap around we have to start at the beginning.
  673. */
  674. if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  675. dep->busy_slot = 1;
  676. dep->free_slot = 1;
  677. } else {
  678. dep->busy_slot = 0;
  679. dep->free_slot = 0;
  680. }
  681. }
  682. /* The last TRB is a link TRB, not used for xfer */
  683. if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
  684. return;
  685. list_for_each_entry_safe(req, n, &dep->request_list, list) {
  686. unsigned length;
  687. dma_addr_t dma;
  688. dma = req->request.dma;
  689. length = req->request.length;
  690. dwc3_prepare_one_trb(dep, req, dma, length,
  691. true, false, 0);
  692. break;
  693. }
  694. }
  695. static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
  696. int start_new)
  697. {
  698. struct dwc3_gadget_ep_cmd_params params;
  699. struct dwc3_request *req;
  700. struct dwc3 *dwc = dep->dwc;
  701. int ret;
  702. u32 cmd;
  703. if (start_new && (dep->flags & DWC3_EP_BUSY)) {
  704. dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
  705. return -EBUSY;
  706. }
  707. dep->flags &= ~DWC3_EP_PENDING_REQUEST;
  708. /*
  709. * If we are getting here after a short-out-packet we don't enqueue any
  710. * new requests as we try to set the IOC bit only on the last request.
  711. */
  712. if (start_new) {
  713. if (list_empty(&dep->req_queued))
  714. dwc3_prepare_trbs(dep, start_new);
  715. /* req points to the first request which will be sent */
  716. req = next_request(&dep->req_queued);
  717. } else {
  718. dwc3_prepare_trbs(dep, start_new);
  719. /*
  720. * req points to the first request where HWO changed from 0 to 1
  721. */
  722. req = next_request(&dep->req_queued);
  723. }
  724. if (!req) {
  725. dep->flags |= DWC3_EP_PENDING_REQUEST;
  726. return 0;
  727. }
  728. memset(&params, 0, sizeof(params));
  729. if (start_new) {
  730. params.param0 = upper_32_bits(req->trb_dma);
  731. params.param1 = lower_32_bits(req->trb_dma);
  732. cmd = DWC3_DEPCMD_STARTTRANSFER;
  733. } else {
  734. cmd = DWC3_DEPCMD_UPDATETRANSFER;
  735. }
  736. cmd |= DWC3_DEPCMD_PARAM(cmd_param);
  737. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
  738. if (ret < 0) {
  739. dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
  740. /*
  741. * FIXME we need to iterate over the list of requests
  742. * here and stop, unmap, free and del each of the linked
  743. * requests instead of what we do now.
  744. */
  745. usb_gadget_unmap_request(&dwc->gadget, &req->request,
  746. req->direction);
  747. list_del(&req->list);
  748. return ret;
  749. }
  750. dep->flags |= DWC3_EP_BUSY;
  751. if (start_new) {
  752. dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
  753. dep->number);
  754. WARN_ON_ONCE(!dep->resource_index);
  755. }
  756. return 0;
  757. }
  758. static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
  759. struct dwc3_ep *dep, u32 cur_uf)
  760. {
  761. u32 uf;
  762. if (list_empty(&dep->request_list)) {
  763. dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
  764. dep->name);
  765. dep->flags |= DWC3_EP_PENDING_REQUEST;
  766. return;
  767. }
  768. /* 4 micro frames in the future */
  769. uf = cur_uf + dep->interval * 4;
  770. __dwc3_gadget_kick_transfer(dep, uf, 1);
  771. }
  772. static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
  773. struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
  774. {
  775. u32 cur_uf, mask;
  776. mask = ~(dep->interval - 1);
  777. cur_uf = event->parameters & mask;
  778. __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
  779. }
  780. static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
  781. {
  782. struct dwc3 *dwc = dep->dwc;
  783. int ret;
  784. req->request.actual = 0;
  785. req->request.status = -EINPROGRESS;
  786. req->direction = dep->direction;
  787. req->epnum = dep->number;
  788. /*
  789. * DWC3 hangs on OUT requests smaller than maxpacket size,
  790. * so HACK the request length
  791. */
  792. if (dep->direction == 0 &&
  793. req->request.length < dep->endpoint.maxpacket)
  794. req->request.length = dep->endpoint.maxpacket;
  795. /*
  796. * We only add to our list of requests now and
  797. * start consuming the list once we get XferNotReady
  798. * IRQ.
  799. *
  800. * That way, we avoid doing anything that we don't need
  801. * to do now and defer it until the point we receive a
  802. * particular token from the Host side.
  803. *
  804. * This will also avoid Host cancelling URBs due to too
  805. * many NAKs.
  806. */
  807. ret = usb_gadget_map_request(&dwc->gadget, &req->request,
  808. dep->direction);
  809. if (ret)
  810. return ret;
  811. list_add_tail(&req->list, &dep->request_list);
  812. /*
  813. * There are a few special cases:
  814. *
  815. * 1. XferNotReady with empty list of requests. We need to kick the
  816. * transfer here in that situation, otherwise we will be NAKing
  817. * forever. If we get XferNotReady before gadget driver has a
  818. * chance to queue a request, we will ACK the IRQ but won't be
  819. * able to receive the data until the next request is queued.
  820. * The following code is handling exactly that.
  821. *
  822. */
  823. if (dep->flags & DWC3_EP_PENDING_REQUEST) {
  824. /*
  825. * If xfernotready is already elapsed and it is a case
  826. * of isoc transfer, then issue END TRANSFER, so that
  827. * you can receive xfernotready again and can have
  828. * notion of current microframe.
  829. */
  830. if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  831. if (list_empty(&dep->req_queued)) {
  832. dwc3_stop_active_transfer(dwc, dep->number, true);
  833. dep->flags = DWC3_EP_ENABLED;
  834. }
  835. return 0;
  836. }
  837. ret = __dwc3_gadget_kick_transfer(dep, 0, true);
  838. if (ret && ret != -EBUSY)
  839. dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
  840. dep->name);
  841. return ret;
  842. }
  843. /*
  844. * 2. XferInProgress on Isoc EP with an active transfer. We need to
  845. * kick the transfer here after queuing a request, otherwise the
  846. * core may not see the modified TRB(s).
  847. */
  848. if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
  849. (dep->flags & DWC3_EP_BUSY) &&
  850. !(dep->flags & DWC3_EP_MISSED_ISOC)) {
  851. WARN_ON_ONCE(!dep->resource_index);
  852. ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
  853. false);
  854. if (ret && ret != -EBUSY)
  855. dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
  856. dep->name);
  857. return ret;
  858. }
  859. /*
  860. * 4. Stream Capable Bulk Endpoints. We need to start the transfer
  861. * right away, otherwise host will not know we have streams to be
  862. * handled.
  863. */
  864. if (dep->stream_capable) {
  865. int ret;
  866. ret = __dwc3_gadget_kick_transfer(dep, 0, true);
  867. if (ret && ret != -EBUSY) {
  868. dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
  869. dep->name);
  870. }
  871. }
  872. return 0;
  873. }
  874. static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
  875. gfp_t gfp_flags)
  876. {
  877. struct dwc3_request *req = to_dwc3_request(request);
  878. struct dwc3_ep *dep = to_dwc3_ep(ep);
  879. unsigned long flags;
  880. int ret;
  881. spin_lock_irqsave(&dwc->lock, flags);
  882. if (!dep->endpoint.desc) {
  883. dev_dbg(dep->dwc->dev,
  884. "trying to queue request %p to disabled %s\n", request,
  885. ep->name);
  886. ret = -ESHUTDOWN;
  887. goto out;
  888. }
  889. if (req->dep != dep) {
  890. WARN(true, "request %p belongs to '%s'\n", request,
  891. req->dep->name);
  892. ret = -EINVAL;
  893. goto out;
  894. }
  895. dev_vdbg(dep->dwc->dev, "queing request %p to %s length %d\n",
  896. request, ep->name, request->length);
  897. ret = __dwc3_gadget_ep_queue(dep, req);
  898. out:
  899. spin_unlock_irqrestore(&dwc->lock, flags);
  900. return ret;
  901. }
  902. static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
  903. struct usb_request *request)
  904. {
  905. struct dwc3_request *req = to_dwc3_request(request);
  906. struct dwc3_request *r = NULL;
  907. struct dwc3_ep *dep = to_dwc3_ep(ep);
  908. struct dwc3 *dwc = dep->dwc;
  909. unsigned long flags;
  910. int ret = 0;
  911. spin_lock_irqsave(&dwc->lock, flags);
  912. list_for_each_entry(r, &dep->request_list, list) {
  913. if (r == req)
  914. break;
  915. }
  916. if (r != req) {
  917. list_for_each_entry(r, &dep->req_queued, list) {
  918. if (r == req)
  919. break;
  920. }
  921. if (r == req) {
  922. /* wait until it is processed */
  923. dwc3_stop_active_transfer(dwc, dep->number, true);
  924. goto out1;
  925. }
  926. dev_err(dwc->dev, "request %p was not queued to %s\n",
  927. request, ep->name);
  928. ret = -EINVAL;
  929. goto out0;
  930. }
  931. out1:
  932. /* giveback the request */
  933. dwc3_gadget_giveback(dep, req, -ECONNRESET);
  934. out0:
  935. spin_unlock_irqrestore(&dwc->lock, flags);
  936. return ret;
  937. }
  938. int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
  939. {
  940. struct dwc3_gadget_ep_cmd_params params;
  941. struct dwc3 *dwc = dep->dwc;
  942. int ret;
  943. if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  944. dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
  945. return -EINVAL;
  946. }
  947. memset(&params, 0x00, sizeof(params));
  948. if (value) {
  949. if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
  950. (!list_empty(&dep->req_queued) ||
  951. !list_empty(&dep->request_list)))) {
  952. dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
  953. dep->name);
  954. return -EAGAIN;
  955. }
  956. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
  957. DWC3_DEPCMD_SETSTALL, &params);
  958. if (ret)
  959. dev_err(dwc->dev, "failed to set STALL on %s\n",
  960. dep->name);
  961. else
  962. dep->flags |= DWC3_EP_STALL;
  963. } else {
  964. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
  965. DWC3_DEPCMD_CLEARSTALL, &params);
  966. if (ret)
  967. dev_err(dwc->dev, "failed to clear STALL on %s\n",
  968. dep->name);
  969. else
  970. dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
  971. }
  972. return ret;
  973. }
  974. static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
  975. {
  976. struct dwc3_ep *dep = to_dwc3_ep(ep);
  977. unsigned long flags;
  978. int ret;
  979. spin_lock_irqsave(&dwc->lock, flags);
  980. ret = __dwc3_gadget_ep_set_halt(dep, value, false);
  981. spin_unlock_irqrestore(&dwc->lock, flags);
  982. return ret;
  983. }
  984. static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
  985. {
  986. struct dwc3_ep *dep = to_dwc3_ep(ep);
  987. unsigned long flags;
  988. int ret;
  989. spin_lock_irqsave(&dwc->lock, flags);
  990. dep->flags |= DWC3_EP_WEDGE;
  991. if (dep->number == 0 || dep->number == 1)
  992. ret = __dwc3_gadget_ep0_set_halt(ep, 1);
  993. else
  994. ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
  995. spin_unlock_irqrestore(&dwc->lock, flags);
  996. return ret;
  997. }
  998. /* -------------------------------------------------------------------------- */
  999. static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
  1000. .bLength = USB_DT_ENDPOINT_SIZE,
  1001. .bDescriptorType = USB_DT_ENDPOINT,
  1002. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  1003. };
  1004. static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
  1005. .enable = dwc3_gadget_ep0_enable,
  1006. .disable = dwc3_gadget_ep0_disable,
  1007. .alloc_request = dwc3_gadget_ep_alloc_request,
  1008. .free_request = dwc3_gadget_ep_free_request,
  1009. .queue = dwc3_gadget_ep0_queue,
  1010. .dequeue = dwc3_gadget_ep_dequeue,
  1011. .set_halt = dwc3_gadget_ep0_set_halt,
  1012. .set_wedge = dwc3_gadget_ep_set_wedge,
  1013. };
  1014. static const struct usb_ep_ops dwc3_gadget_ep_ops = {
  1015. .enable = dwc3_gadget_ep_enable,
  1016. .disable = dwc3_gadget_ep_disable,
  1017. .alloc_request = dwc3_gadget_ep_alloc_request,
  1018. .free_request = dwc3_gadget_ep_free_request,
  1019. .queue = dwc3_gadget_ep_queue,
  1020. .dequeue = dwc3_gadget_ep_dequeue,
  1021. .set_halt = dwc3_gadget_ep_set_halt,
  1022. .set_wedge = dwc3_gadget_ep_set_wedge,
  1023. };
  1024. /* -------------------------------------------------------------------------- */
  1025. static int dwc3_gadget_get_frame(struct usb_gadget *g)
  1026. {
  1027. struct dwc3 *dwc = gadget_to_dwc(g);
  1028. u32 reg;
  1029. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  1030. return DWC3_DSTS_SOFFN(reg);
  1031. }
  1032. static int dwc3_gadget_wakeup(struct usb_gadget *g)
  1033. {
  1034. struct dwc3 *dwc = gadget_to_dwc(g);
  1035. unsigned long timeout;
  1036. unsigned long flags;
  1037. u32 reg;
  1038. int ret = 0;
  1039. u8 link_state;
  1040. u8 speed;
  1041. spin_lock_irqsave(&dwc->lock, flags);
  1042. /*
  1043. * According to the Databook Remote wakeup request should
  1044. * be issued only when the device is in early suspend state.
  1045. *
  1046. * We can check that via USB Link State bits in DSTS register.
  1047. */
  1048. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  1049. speed = reg & DWC3_DSTS_CONNECTSPD;
  1050. if (speed == DWC3_DSTS_SUPERSPEED) {
  1051. dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
  1052. ret = -EINVAL;
  1053. goto out;
  1054. }
  1055. link_state = DWC3_DSTS_USBLNKST(reg);
  1056. switch (link_state) {
  1057. case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
  1058. case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
  1059. break;
  1060. default:
  1061. dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
  1062. link_state);
  1063. ret = -EINVAL;
  1064. goto out;
  1065. }
  1066. ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
  1067. if (ret < 0) {
  1068. dev_err(dwc->dev, "failed to put link in Recovery\n");
  1069. goto out;
  1070. }
  1071. /* Recent versions do this automatically */
  1072. if (dwc->revision < DWC3_REVISION_194A) {
  1073. /* write zeroes to Link Change Request */
  1074. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1075. reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
  1076. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1077. }
  1078. /* poll until Link State changes to ON */
  1079. timeout = 1000;
  1080. while (timeout--) {
  1081. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  1082. /* in HS, means ON */
  1083. if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
  1084. break;
  1085. }
  1086. if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
  1087. dev_err(dwc->dev, "failed to send remote wakeup\n");
  1088. ret = -EINVAL;
  1089. }
  1090. out:
  1091. spin_unlock_irqrestore(&dwc->lock, flags);
  1092. return ret;
  1093. }
  1094. static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
  1095. int is_selfpowered)
  1096. {
  1097. struct dwc3 *dwc = gadget_to_dwc(g);
  1098. unsigned long flags;
  1099. spin_lock_irqsave(&dwc->lock, flags);
  1100. dwc->is_selfpowered = !!is_selfpowered;
  1101. spin_unlock_irqrestore(&dwc->lock, flags);
  1102. return 0;
  1103. }
  1104. static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
  1105. {
  1106. u32 reg;
  1107. u32 timeout = 500;
  1108. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1109. if (is_on) {
  1110. if (dwc->revision <= DWC3_REVISION_187A) {
  1111. reg &= ~DWC3_DCTL_TRGTULST_MASK;
  1112. reg |= DWC3_DCTL_TRGTULST_RX_DET;
  1113. }
  1114. if (dwc->revision >= DWC3_REVISION_194A)
  1115. reg &= ~DWC3_DCTL_KEEP_CONNECT;
  1116. reg |= DWC3_DCTL_RUN_STOP;
  1117. if (dwc->has_hibernation)
  1118. reg |= DWC3_DCTL_KEEP_CONNECT;
  1119. dwc->pullups_connected = true;
  1120. } else {
  1121. reg &= ~DWC3_DCTL_RUN_STOP;
  1122. if (dwc->has_hibernation && !suspend)
  1123. reg &= ~DWC3_DCTL_KEEP_CONNECT;
  1124. dwc->pullups_connected = false;
  1125. }
  1126. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1127. do {
  1128. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  1129. if (is_on) {
  1130. if (!(reg & DWC3_DSTS_DEVCTRLHLT))
  1131. break;
  1132. } else {
  1133. if (reg & DWC3_DSTS_DEVCTRLHLT)
  1134. break;
  1135. }
  1136. timeout--;
  1137. if (!timeout)
  1138. return -ETIMEDOUT;
  1139. udelay(1);
  1140. } while (1);
  1141. dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
  1142. dwc->gadget_driver
  1143. ? dwc->gadget_driver->function : "no-function",
  1144. is_on ? "connect" : "disconnect");
  1145. return 0;
  1146. }
  1147. static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
  1148. {
  1149. struct dwc3 *dwc = gadget_to_dwc(g);
  1150. unsigned long flags;
  1151. int ret;
  1152. is_on = !!is_on;
  1153. spin_lock_irqsave(&dwc->lock, flags);
  1154. ret = dwc3_gadget_run_stop(dwc, is_on, false);
  1155. spin_unlock_irqrestore(&dwc->lock, flags);
  1156. return ret;
  1157. }
  1158. static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
  1159. {
  1160. u32 reg;
  1161. /* Enable all but Start and End of Frame IRQs */
  1162. reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
  1163. DWC3_DEVTEN_EVNTOVERFLOWEN |
  1164. DWC3_DEVTEN_CMDCMPLTEN |
  1165. DWC3_DEVTEN_ERRTICERREN |
  1166. DWC3_DEVTEN_WKUPEVTEN |
  1167. DWC3_DEVTEN_ULSTCNGEN |
  1168. DWC3_DEVTEN_CONNECTDONEEN |
  1169. DWC3_DEVTEN_USBRSTEN |
  1170. DWC3_DEVTEN_DISCONNEVTEN);
  1171. dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
  1172. }
  1173. static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
  1174. {
  1175. /* mask all interrupts */
  1176. dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
  1177. }
  1178. static int dwc3_gadget_start(struct usb_gadget *g,
  1179. struct usb_gadget_driver *driver)
  1180. {
  1181. struct dwc3 *dwc = gadget_to_dwc(g);
  1182. struct dwc3_ep *dep;
  1183. unsigned long flags;
  1184. int ret = 0;
  1185. u32 reg;
  1186. spin_lock_irqsave(&dwc->lock, flags);
  1187. if (dwc->gadget_driver) {
  1188. dev_err(dwc->dev, "%s is already bound to %s\n",
  1189. dwc->gadget.name,
  1190. dwc->gadget_driver->function);
  1191. ret = -EBUSY;
  1192. goto err1;
  1193. }
  1194. dwc->gadget_driver = driver;
  1195. reg = dwc3_readl(dwc->regs, DWC3_DCFG);
  1196. reg &= ~(DWC3_DCFG_SPEED_MASK);
  1197. /**
  1198. * WORKAROUND: DWC3 revision < 2.20a have an issue
  1199. * which would cause metastability state on Run/Stop
  1200. * bit if we try to force the IP to USB2-only mode.
  1201. *
  1202. * Because of that, we cannot configure the IP to any
  1203. * speed other than the SuperSpeed
  1204. *
  1205. * Refers to:
  1206. *
  1207. * STAR#9000525659: Clock Domain Crossing on DCTL in
  1208. * USB 2.0 Mode
  1209. */
  1210. if (dwc->revision < DWC3_REVISION_220A) {
  1211. reg |= DWC3_DCFG_SUPERSPEED;
  1212. } else {
  1213. switch (dwc->maximum_speed) {
  1214. case USB_SPEED_LOW:
  1215. reg |= DWC3_DSTS_LOWSPEED;
  1216. break;
  1217. case USB_SPEED_FULL:
  1218. reg |= DWC3_DSTS_FULLSPEED1;
  1219. break;
  1220. case USB_SPEED_HIGH:
  1221. reg |= DWC3_DSTS_HIGHSPEED;
  1222. break;
  1223. case USB_SPEED_SUPER: /* FALLTHROUGH */
  1224. case USB_SPEED_UNKNOWN: /* FALTHROUGH */
  1225. default:
  1226. reg |= DWC3_DSTS_SUPERSPEED;
  1227. }
  1228. }
  1229. dwc3_writel(dwc->regs, DWC3_DCFG, reg);
  1230. dwc->start_config_issued = false;
  1231. /* Start with SuperSpeed Default */
  1232. dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
  1233. dep = dwc->eps[0];
  1234. ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
  1235. false);
  1236. if (ret) {
  1237. dev_err(dwc->dev, "failed to enable %s\n", dep->name);
  1238. goto err2;
  1239. }
  1240. dep = dwc->eps[1];
  1241. ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
  1242. false);
  1243. if (ret) {
  1244. dev_err(dwc->dev, "failed to enable %s\n", dep->name);
  1245. goto err3;
  1246. }
  1247. /* begin to receive SETUP packets */
  1248. dwc->ep0state = EP0_SETUP_PHASE;
  1249. dwc3_ep0_out_start(dwc);
  1250. dwc3_gadget_enable_irq(dwc);
  1251. spin_unlock_irqrestore(&dwc->lock, flags);
  1252. return 0;
  1253. err3:
  1254. __dwc3_gadget_ep_disable(dwc->eps[0]);
  1255. err2:
  1256. dwc->gadget_driver = NULL;
  1257. err1:
  1258. spin_unlock_irqrestore(&dwc->lock, flags);
  1259. return ret;
  1260. }
  1261. static int dwc3_gadget_stop(struct usb_gadget *g)
  1262. {
  1263. struct dwc3 *dwc = gadget_to_dwc(g);
  1264. unsigned long flags;
  1265. spin_lock_irqsave(&dwc->lock, flags);
  1266. dwc3_gadget_disable_irq(dwc);
  1267. __dwc3_gadget_ep_disable(dwc->eps[0]);
  1268. __dwc3_gadget_ep_disable(dwc->eps[1]);
  1269. dwc->gadget_driver = NULL;
  1270. spin_unlock_irqrestore(&dwc->lock, flags);
  1271. return 0;
  1272. }
  1273. static const struct usb_gadget_ops dwc3_gadget_ops = {
  1274. .get_frame = dwc3_gadget_get_frame,
  1275. .wakeup = dwc3_gadget_wakeup,
  1276. .set_selfpowered = dwc3_gadget_set_selfpowered,
  1277. .pullup = dwc3_gadget_pullup,
  1278. .udc_start = dwc3_gadget_start,
  1279. .udc_stop = dwc3_gadget_stop,
  1280. };
  1281. /* -------------------------------------------------------------------------- */
  1282. static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
  1283. u8 num, u32 direction)
  1284. {
  1285. struct dwc3_ep *dep;
  1286. u8 i;
  1287. for (i = 0; i < num; i++) {
  1288. u8 epnum = (i << 1) | (!!direction);
  1289. dep = kzalloc(sizeof(*dep), GFP_KERNEL);
  1290. if (!dep)
  1291. return -ENOMEM;
  1292. dep->dwc = dwc;
  1293. dep->number = epnum;
  1294. dep->direction = !!direction;
  1295. dwc->eps[epnum] = dep;
  1296. snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
  1297. (epnum & 1) ? "in" : "out");
  1298. dep->endpoint.name = dep->name;
  1299. dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
  1300. if (epnum == 0 || epnum == 1) {
  1301. usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
  1302. dep->endpoint.maxburst = 1;
  1303. dep->endpoint.ops = &dwc3_gadget_ep0_ops;
  1304. if (!epnum)
  1305. dwc->gadget.ep0 = &dep->endpoint;
  1306. } else {
  1307. int ret;
  1308. usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
  1309. dep->endpoint.max_streams = 15;
  1310. dep->endpoint.ops = &dwc3_gadget_ep_ops;
  1311. list_add_tail(&dep->endpoint.ep_list,
  1312. &dwc->gadget.ep_list);
  1313. ret = dwc3_alloc_trb_pool(dep);
  1314. if (ret)
  1315. return ret;
  1316. }
  1317. INIT_LIST_HEAD(&dep->request_list);
  1318. INIT_LIST_HEAD(&dep->req_queued);
  1319. }
  1320. return 0;
  1321. }
  1322. static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
  1323. {
  1324. int ret;
  1325. INIT_LIST_HEAD(&dwc->gadget.ep_list);
  1326. ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
  1327. if (ret < 0) {
  1328. dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
  1329. return ret;
  1330. }
  1331. ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
  1332. if (ret < 0) {
  1333. dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
  1334. return ret;
  1335. }
  1336. return 0;
  1337. }
  1338. static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
  1339. {
  1340. struct dwc3_ep *dep;
  1341. u8 epnum;
  1342. for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
  1343. dep = dwc->eps[epnum];
  1344. if (!dep)
  1345. continue;
  1346. /*
  1347. * Physical endpoints 0 and 1 are special; they form the
  1348. * bi-directional USB endpoint 0.
  1349. *
  1350. * For those two physical endpoints, we don't allocate a TRB
  1351. * pool nor do we add them the endpoints list. Due to that, we
  1352. * shouldn't do these two operations otherwise we would end up
  1353. * with all sorts of bugs when removing dwc3.ko.
  1354. */
  1355. if (epnum != 0 && epnum != 1) {
  1356. dwc3_free_trb_pool(dep);
  1357. list_del(&dep->endpoint.ep_list);
  1358. }
  1359. kfree(dep);
  1360. }
  1361. }
  1362. /* -------------------------------------------------------------------------- */
  1363. static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
  1364. struct dwc3_request *req, struct dwc3_trb *trb,
  1365. const struct dwc3_event_depevt *event, int status)
  1366. {
  1367. unsigned int count;
  1368. unsigned int s_pkt = 0;
  1369. unsigned int trb_status;
  1370. if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
  1371. /*
  1372. * We continue despite the error. There is not much we
  1373. * can do. If we don't clean it up we loop forever. If
  1374. * we skip the TRB then it gets overwritten after a
  1375. * while since we use them in a ring buffer. A BUG()
  1376. * would help. Lets hope that if this occurs, someone
  1377. * fixes the root cause instead of looking away :)
  1378. */
  1379. dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
  1380. dep->name, trb);
  1381. count = trb->size & DWC3_TRB_SIZE_MASK;
  1382. if (dep->direction) {
  1383. if (count) {
  1384. trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
  1385. if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
  1386. dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
  1387. dep->name);
  1388. /*
  1389. * If missed isoc occurred and there is
  1390. * no request queued then issue END
  1391. * TRANSFER, so that core generates
  1392. * next xfernotready and we will issue
  1393. * a fresh START TRANSFER.
  1394. * If there are still queued request
  1395. * then wait, do not issue either END
  1396. * or UPDATE TRANSFER, just attach next
  1397. * request in request_list during
  1398. * giveback.If any future queued request
  1399. * is successfully transferred then we
  1400. * will issue UPDATE TRANSFER for all
  1401. * request in the request_list.
  1402. */
  1403. dep->flags |= DWC3_EP_MISSED_ISOC;
  1404. } else {
  1405. dev_err(dwc->dev, "incomplete IN transfer %s\n",
  1406. dep->name);
  1407. status = -ECONNRESET;
  1408. }
  1409. } else {
  1410. dep->flags &= ~DWC3_EP_MISSED_ISOC;
  1411. }
  1412. } else {
  1413. if (count && (event->status & DEPEVT_STATUS_SHORT))
  1414. s_pkt = 1;
  1415. }
  1416. /*
  1417. * We assume here we will always receive the entire data block
  1418. * which we should receive. Meaning, if we program RX to
  1419. * receive 4K but we receive only 2K, we assume that's all we
  1420. * should receive and we simply bounce the request back to the
  1421. * gadget driver for further processing.
  1422. */
  1423. req->request.actual += req->request.length - count;
  1424. if (s_pkt)
  1425. return 1;
  1426. if ((event->status & DEPEVT_STATUS_LST) &&
  1427. (trb->ctrl & (DWC3_TRB_CTRL_LST |
  1428. DWC3_TRB_CTRL_HWO)))
  1429. return 1;
  1430. if ((event->status & DEPEVT_STATUS_IOC) &&
  1431. (trb->ctrl & DWC3_TRB_CTRL_IOC))
  1432. return 1;
  1433. return 0;
  1434. }
  1435. static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
  1436. const struct dwc3_event_depevt *event, int status)
  1437. {
  1438. struct dwc3_request *req;
  1439. struct dwc3_trb *trb;
  1440. unsigned int slot;
  1441. req = next_request(&dep->req_queued);
  1442. if (!req) {
  1443. WARN_ON_ONCE(1);
  1444. return 1;
  1445. }
  1446. slot = req->start_slot;
  1447. if ((slot == DWC3_TRB_NUM - 1) &&
  1448. usb_endpoint_xfer_isoc(dep->endpoint.desc))
  1449. slot++;
  1450. slot %= DWC3_TRB_NUM;
  1451. trb = &dep->trb_pool[slot];
  1452. dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
  1453. __dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
  1454. dwc3_gadget_giveback(dep, req, status);
  1455. if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
  1456. list_empty(&dep->req_queued)) {
  1457. if (list_empty(&dep->request_list)) {
  1458. /*
  1459. * If there is no entry in request list then do
  1460. * not issue END TRANSFER now. Just set PENDING
  1461. * flag, so that END TRANSFER is issued when an
  1462. * entry is added into request list.
  1463. */
  1464. dep->flags = DWC3_EP_PENDING_REQUEST;
  1465. } else {
  1466. dwc3_stop_active_transfer(dwc, dep->number, true);
  1467. dep->flags = DWC3_EP_ENABLED;
  1468. }
  1469. return 1;
  1470. }
  1471. return 1;
  1472. }
  1473. static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
  1474. struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
  1475. {
  1476. unsigned status = 0;
  1477. int clean_busy;
  1478. if (event->status & DEPEVT_STATUS_BUSERR)
  1479. status = -ECONNRESET;
  1480. clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
  1481. if (clean_busy)
  1482. dep->flags &= ~DWC3_EP_BUSY;
  1483. /*
  1484. * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
  1485. * See dwc3_gadget_linksts_change_interrupt() for 1st half.
  1486. */
  1487. if (dwc->revision < DWC3_REVISION_183A) {
  1488. u32 reg;
  1489. int i;
  1490. for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
  1491. dep = dwc->eps[i];
  1492. if (!(dep->flags & DWC3_EP_ENABLED))
  1493. continue;
  1494. if (!list_empty(&dep->req_queued))
  1495. return;
  1496. }
  1497. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1498. reg |= dwc->u1u2;
  1499. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1500. dwc->u1u2 = 0;
  1501. }
  1502. }
  1503. static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
  1504. const struct dwc3_event_depevt *event)
  1505. {
  1506. struct dwc3_ep *dep;
  1507. u8 epnum = event->endpoint_number;
  1508. dep = dwc->eps[epnum];
  1509. if (!(dep->flags & DWC3_EP_ENABLED))
  1510. return;
  1511. if (epnum == 0 || epnum == 1) {
  1512. dwc3_ep0_interrupt(dwc, event);
  1513. return;
  1514. }
  1515. switch (event->endpoint_event) {
  1516. case DWC3_DEPEVT_XFERCOMPLETE:
  1517. dep->resource_index = 0;
  1518. if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  1519. dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
  1520. dep->name);
  1521. return;
  1522. }
  1523. dwc3_endpoint_transfer_complete(dwc, dep, event);
  1524. break;
  1525. case DWC3_DEPEVT_XFERINPROGRESS:
  1526. dwc3_endpoint_transfer_complete(dwc, dep, event);
  1527. break;
  1528. case DWC3_DEPEVT_XFERNOTREADY:
  1529. if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
  1530. dwc3_gadget_start_isoc(dwc, dep, event);
  1531. } else {
  1532. int ret;
  1533. dev_vdbg(dwc->dev, "%s: reason %s\n",
  1534. dep->name, event->status &
  1535. DEPEVT_STATUS_TRANSFER_ACTIVE
  1536. ? "Transfer Active"
  1537. : "Transfer Not Active");
  1538. ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
  1539. if (!ret || ret == -EBUSY)
  1540. return;
  1541. dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
  1542. dep->name);
  1543. }
  1544. break;
  1545. case DWC3_DEPEVT_STREAMEVT:
  1546. if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
  1547. dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
  1548. dep->name);
  1549. return;
  1550. }
  1551. switch (event->status) {
  1552. case DEPEVT_STREAMEVT_FOUND:
  1553. dev_vdbg(dwc->dev, "Stream %d found and started\n",
  1554. event->parameters);
  1555. break;
  1556. case DEPEVT_STREAMEVT_NOTFOUND:
  1557. /* FALLTHROUGH */
  1558. default:
  1559. dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
  1560. }
  1561. break;
  1562. case DWC3_DEPEVT_RXTXFIFOEVT:
  1563. dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
  1564. break;
  1565. case DWC3_DEPEVT_EPCMDCMPLT:
  1566. dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
  1567. break;
  1568. }
  1569. }
  1570. static void dwc3_disconnect_gadget(struct dwc3 *dwc)
  1571. {
  1572. if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
  1573. spin_unlock(&dwc->lock);
  1574. dwc->gadget_driver->disconnect(&dwc->gadget);
  1575. spin_lock(&dwc->lock);
  1576. }
  1577. }
  1578. static void dwc3_suspend_gadget(struct dwc3 *dwc)
  1579. {
  1580. if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
  1581. spin_unlock(&dwc->lock);
  1582. dwc->gadget_driver->suspend(&dwc->gadget);
  1583. spin_lock(&dwc->lock);
  1584. }
  1585. }
  1586. static void dwc3_resume_gadget(struct dwc3 *dwc)
  1587. {
  1588. if (dwc->gadget_driver && dwc->gadget_driver->resume) {
  1589. spin_unlock(&dwc->lock);
  1590. dwc->gadget_driver->resume(&dwc->gadget);
  1591. }
  1592. }
  1593. static void dwc3_reset_gadget(struct dwc3 *dwc)
  1594. {
  1595. if (!dwc->gadget_driver)
  1596. return;
  1597. if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
  1598. spin_unlock(&dwc->lock);
  1599. usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
  1600. spin_lock(&dwc->lock);
  1601. }
  1602. }
  1603. static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
  1604. {
  1605. struct dwc3_ep *dep;
  1606. struct dwc3_gadget_ep_cmd_params params;
  1607. u32 cmd;
  1608. int ret;
  1609. dep = dwc->eps[epnum];
  1610. if (!dep->resource_index)
  1611. return;
  1612. /*
  1613. * NOTICE: We are violating what the Databook says about the
  1614. * EndTransfer command. Ideally we would _always_ wait for the
  1615. * EndTransfer Command Completion IRQ, but that's causing too
  1616. * much trouble synchronizing between us and gadget driver.
  1617. *
  1618. * We have discussed this with the IP Provider and it was
  1619. * suggested to giveback all requests here, but give HW some
  1620. * extra time to synchronize with the interconnect. We're using
  1621. * an arbitraty 100us delay for that.
  1622. *
  1623. * Note also that a similar handling was tested by Synopsys
  1624. * (thanks a lot Paul) and nothing bad has come out of it.
  1625. * In short, what we're doing is:
  1626. *
  1627. * - Issue EndTransfer WITH CMDIOC bit set
  1628. * - Wait 100us
  1629. */
  1630. cmd = DWC3_DEPCMD_ENDTRANSFER;
  1631. cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
  1632. cmd |= DWC3_DEPCMD_CMDIOC;
  1633. cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
  1634. memset(&params, 0, sizeof(params));
  1635. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
  1636. WARN_ON_ONCE(ret);
  1637. dep->resource_index = 0;
  1638. dep->flags &= ~DWC3_EP_BUSY;
  1639. udelay(100);
  1640. }
  1641. static void dwc3_stop_active_transfers(struct dwc3 *dwc)
  1642. {
  1643. u32 epnum;
  1644. for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
  1645. struct dwc3_ep *dep;
  1646. dep = dwc->eps[epnum];
  1647. if (!dep)
  1648. continue;
  1649. if (!(dep->flags & DWC3_EP_ENABLED))
  1650. continue;
  1651. dwc3_remove_requests(dwc, dep);
  1652. }
  1653. }
  1654. static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
  1655. {
  1656. u32 epnum;
  1657. for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
  1658. struct dwc3_ep *dep;
  1659. struct dwc3_gadget_ep_cmd_params params;
  1660. int ret;
  1661. dep = dwc->eps[epnum];
  1662. if (!dep)
  1663. continue;
  1664. if (!(dep->flags & DWC3_EP_STALL))
  1665. continue;
  1666. dep->flags &= ~DWC3_EP_STALL;
  1667. memset(&params, 0, sizeof(params));
  1668. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
  1669. DWC3_DEPCMD_CLEARSTALL, &params);
  1670. WARN_ON_ONCE(ret);
  1671. }
  1672. }
  1673. static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
  1674. {
  1675. int reg;
  1676. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1677. reg &= ~DWC3_DCTL_INITU1ENA;
  1678. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1679. reg &= ~DWC3_DCTL_INITU2ENA;
  1680. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1681. dwc3_disconnect_gadget(dwc);
  1682. dwc->start_config_issued = false;
  1683. dwc->gadget.speed = USB_SPEED_UNKNOWN;
  1684. dwc->setup_packet_pending = false;
  1685. usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
  1686. }
  1687. static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
  1688. {
  1689. u32 reg;
  1690. /*
  1691. * WORKAROUND: DWC3 revisions <1.88a have an issue which
  1692. * would cause a missing Disconnect Event if there's a
  1693. * pending Setup Packet in the FIFO.
  1694. *
  1695. * There's no suggested workaround on the official Bug
  1696. * report, which states that "unless the driver/application
  1697. * is doing any special handling of a disconnect event,
  1698. * there is no functional issue".
  1699. *
  1700. * Unfortunately, it turns out that we _do_ some special
  1701. * handling of a disconnect event, namely complete all
  1702. * pending transfers, notify gadget driver of the
  1703. * disconnection, and so on.
  1704. *
  1705. * Our suggested workaround is to follow the Disconnect
  1706. * Event steps here, instead, based on a setup_packet_pending
  1707. * flag. Such flag gets set whenever we have a XferNotReady
  1708. * event on EP0 and gets cleared on XferComplete for the
  1709. * same endpoint.
  1710. *
  1711. * Refers to:
  1712. *
  1713. * STAR#9000466709: RTL: Device : Disconnect event not
  1714. * generated if setup packet pending in FIFO
  1715. */
  1716. if (dwc->revision < DWC3_REVISION_188A) {
  1717. if (dwc->setup_packet_pending)
  1718. dwc3_gadget_disconnect_interrupt(dwc);
  1719. }
  1720. dwc3_reset_gadget(dwc);
  1721. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1722. reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  1723. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1724. dwc->test_mode = false;
  1725. dwc3_stop_active_transfers(dwc);
  1726. dwc3_clear_stall_all_ep(dwc);
  1727. dwc->start_config_issued = false;
  1728. /* Reset device address to zero */
  1729. reg = dwc3_readl(dwc->regs, DWC3_DCFG);
  1730. reg &= ~(DWC3_DCFG_DEVADDR_MASK);
  1731. dwc3_writel(dwc->regs, DWC3_DCFG, reg);
  1732. }
  1733. static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
  1734. {
  1735. u32 reg;
  1736. u32 usb30_clock = DWC3_GCTL_CLK_BUS;
  1737. /*
  1738. * We change the clock only at SS but I dunno why I would want to do
  1739. * this. Maybe it becomes part of the power saving plan.
  1740. */
  1741. if (speed != DWC3_DSTS_SUPERSPEED)
  1742. return;
  1743. /*
  1744. * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
  1745. * each time on Connect Done.
  1746. */
  1747. if (!usb30_clock)
  1748. return;
  1749. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  1750. reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
  1751. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  1752. }
  1753. static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
  1754. {
  1755. struct dwc3_ep *dep;
  1756. int ret;
  1757. u32 reg;
  1758. u8 speed;
  1759. reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  1760. speed = reg & DWC3_DSTS_CONNECTSPD;
  1761. dwc->speed = speed;
  1762. dwc3_update_ram_clk_sel(dwc, speed);
  1763. switch (speed) {
  1764. case DWC3_DCFG_SUPERSPEED:
  1765. /*
  1766. * WORKAROUND: DWC3 revisions <1.90a have an issue which
  1767. * would cause a missing USB3 Reset event.
  1768. *
  1769. * In such situations, we should force a USB3 Reset
  1770. * event by calling our dwc3_gadget_reset_interrupt()
  1771. * routine.
  1772. *
  1773. * Refers to:
  1774. *
  1775. * STAR#9000483510: RTL: SS : USB3 reset event may
  1776. * not be generated always when the link enters poll
  1777. */
  1778. if (dwc->revision < DWC3_REVISION_190A)
  1779. dwc3_gadget_reset_interrupt(dwc);
  1780. dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
  1781. dwc->gadget.ep0->maxpacket = 512;
  1782. dwc->gadget.speed = USB_SPEED_SUPER;
  1783. break;
  1784. case DWC3_DCFG_HIGHSPEED:
  1785. dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
  1786. dwc->gadget.ep0->maxpacket = 64;
  1787. dwc->gadget.speed = USB_SPEED_HIGH;
  1788. break;
  1789. case DWC3_DCFG_FULLSPEED2:
  1790. case DWC3_DCFG_FULLSPEED1:
  1791. dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
  1792. dwc->gadget.ep0->maxpacket = 64;
  1793. dwc->gadget.speed = USB_SPEED_FULL;
  1794. break;
  1795. case DWC3_DCFG_LOWSPEED:
  1796. dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
  1797. dwc->gadget.ep0->maxpacket = 8;
  1798. dwc->gadget.speed = USB_SPEED_LOW;
  1799. break;
  1800. }
  1801. /* Enable USB2 LPM Capability */
  1802. if ((dwc->revision > DWC3_REVISION_194A)
  1803. && (speed != DWC3_DCFG_SUPERSPEED)) {
  1804. reg = dwc3_readl(dwc->regs, DWC3_DCFG);
  1805. reg |= DWC3_DCFG_LPM_CAP;
  1806. dwc3_writel(dwc->regs, DWC3_DCFG, reg);
  1807. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1808. reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
  1809. reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
  1810. /*
  1811. * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
  1812. * DCFG.LPMCap is set, core responses with an ACK and the
  1813. * BESL value in the LPM token is less than or equal to LPM
  1814. * NYET threshold.
  1815. */
  1816. if (dwc->revision < DWC3_REVISION_240A && dwc->has_lpm_erratum)
  1817. WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
  1818. if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
  1819. reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
  1820. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1821. } else {
  1822. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1823. reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
  1824. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1825. }
  1826. dep = dwc->eps[0];
  1827. ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
  1828. false);
  1829. if (ret) {
  1830. dev_err(dwc->dev, "failed to enable %s\n", dep->name);
  1831. return;
  1832. }
  1833. dep = dwc->eps[1];
  1834. ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
  1835. false);
  1836. if (ret) {
  1837. dev_err(dwc->dev, "failed to enable %s\n", dep->name);
  1838. return;
  1839. }
  1840. /*
  1841. * Configure PHY via GUSB3PIPECTLn if required.
  1842. *
  1843. * Update GTXFIFOSIZn
  1844. *
  1845. * In both cases reset values should be sufficient.
  1846. */
  1847. }
  1848. static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
  1849. {
  1850. /*
  1851. * TODO take core out of low power mode when that's
  1852. * implemented.
  1853. */
  1854. dwc->gadget_driver->resume(&dwc->gadget);
  1855. }
  1856. static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
  1857. unsigned int evtinfo)
  1858. {
  1859. enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
  1860. unsigned int pwropt;
  1861. /*
  1862. * WORKAROUND: DWC3 < 2.50a have an issue when configured without
  1863. * Hibernation mode enabled which would show up when device detects
  1864. * host-initiated U3 exit.
  1865. *
  1866. * In that case, device will generate a Link State Change Interrupt
  1867. * from U3 to RESUME which is only necessary if Hibernation is
  1868. * configured in.
  1869. *
  1870. * There are no functional changes due to such spurious event and we
  1871. * just need to ignore it.
  1872. *
  1873. * Refers to:
  1874. *
  1875. * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
  1876. * operational mode
  1877. */
  1878. pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
  1879. if ((dwc->revision < DWC3_REVISION_250A) &&
  1880. (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
  1881. if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
  1882. (next == DWC3_LINK_STATE_RESUME)) {
  1883. dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
  1884. return;
  1885. }
  1886. }
  1887. /*
  1888. * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
  1889. * on the link partner, the USB session might do multiple entry/exit
  1890. * of low power states before a transfer takes place.
  1891. *
  1892. * Due to this problem, we might experience lower throughput. The
  1893. * suggested workaround is to disable DCTL[12:9] bits if we're
  1894. * transitioning from U1/U2 to U0 and enable those bits again
  1895. * after a transfer completes and there are no pending transfers
  1896. * on any of the enabled endpoints.
  1897. *
  1898. * This is the first half of that workaround.
  1899. *
  1900. * Refers to:
  1901. *
  1902. * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
  1903. * core send LGO_Ux entering U0
  1904. */
  1905. if (dwc->revision < DWC3_REVISION_183A) {
  1906. if (next == DWC3_LINK_STATE_U0) {
  1907. u32 u1u2;
  1908. u32 reg;
  1909. switch (dwc->link_state) {
  1910. case DWC3_LINK_STATE_U1:
  1911. case DWC3_LINK_STATE_U2:
  1912. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  1913. u1u2 = reg & (DWC3_DCTL_INITU2ENA
  1914. | DWC3_DCTL_ACCEPTU2ENA
  1915. | DWC3_DCTL_INITU1ENA
  1916. | DWC3_DCTL_ACCEPTU1ENA);
  1917. if (!dwc->u1u2)
  1918. dwc->u1u2 = reg & u1u2;
  1919. reg &= ~u1u2;
  1920. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  1921. break;
  1922. default:
  1923. /* do nothing */
  1924. break;
  1925. }
  1926. }
  1927. }
  1928. switch (next) {
  1929. case DWC3_LINK_STATE_U1:
  1930. if (dwc->speed == USB_SPEED_SUPER)
  1931. dwc3_suspend_gadget(dwc);
  1932. break;
  1933. case DWC3_LINK_STATE_U2:
  1934. case DWC3_LINK_STATE_U3:
  1935. dwc3_suspend_gadget(dwc);
  1936. break;
  1937. case DWC3_LINK_STATE_RESUME:
  1938. dwc3_resume_gadget(dwc);
  1939. break;
  1940. default:
  1941. /* do nothing */
  1942. break;
  1943. }
  1944. dwc->link_state = next;
  1945. }
  1946. static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
  1947. unsigned int evtinfo)
  1948. {
  1949. unsigned int is_ss = evtinfo & (1UL << 4);
  1950. /**
  1951. * WORKAROUND: DWC3 revison 2.20a with hibernation support
  1952. * have a known issue which can cause USB CV TD.9.23 to fail
  1953. * randomly.
  1954. *
  1955. * Because of this issue, core could generate bogus hibernation
  1956. * events which SW needs to ignore.
  1957. *
  1958. * Refers to:
  1959. *
  1960. * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
  1961. * Device Fallback from SuperSpeed
  1962. */
  1963. if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
  1964. return;
  1965. /* enter hibernation here */
  1966. }
  1967. static void dwc3_gadget_interrupt(struct dwc3 *dwc,
  1968. const struct dwc3_event_devt *event)
  1969. {
  1970. switch (event->type) {
  1971. case DWC3_DEVICE_EVENT_DISCONNECT:
  1972. dwc3_gadget_disconnect_interrupt(dwc);
  1973. break;
  1974. case DWC3_DEVICE_EVENT_RESET:
  1975. dwc3_gadget_reset_interrupt(dwc);
  1976. break;
  1977. case DWC3_DEVICE_EVENT_CONNECT_DONE:
  1978. dwc3_gadget_conndone_interrupt(dwc);
  1979. break;
  1980. case DWC3_DEVICE_EVENT_WAKEUP:
  1981. dwc3_gadget_wakeup_interrupt(dwc);
  1982. break;
  1983. case DWC3_DEVICE_EVENT_HIBER_REQ:
  1984. if (!dwc->has_hibernation) {
  1985. WARN(1 ,"unexpected hibernation event\n");
  1986. break;
  1987. }
  1988. dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
  1989. break;
  1990. case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
  1991. dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
  1992. break;
  1993. case DWC3_DEVICE_EVENT_EOPF:
  1994. dev_vdbg(dwc->dev, "End of Periodic Frame\n");
  1995. break;
  1996. case DWC3_DEVICE_EVENT_SOF:
  1997. dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
  1998. break;
  1999. case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
  2000. dev_vdbg(dwc->dev, "Erratic Error\n");
  2001. break;
  2002. case DWC3_DEVICE_EVENT_CMD_CMPL:
  2003. dev_vdbg(dwc->dev, "Command Complete\n");
  2004. break;
  2005. case DWC3_DEVICE_EVENT_OVERFLOW:
  2006. dev_vdbg(dwc->dev, "Overflow\n");
  2007. break;
  2008. default:
  2009. dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
  2010. }
  2011. }
  2012. static void dwc3_process_event_entry(struct dwc3 *dwc,
  2013. const union dwc3_event *event)
  2014. {
  2015. /* Endpoint IRQ, handle it and return early */
  2016. if (event->type.is_devspec == 0) {
  2017. /* depevt */
  2018. return dwc3_endpoint_interrupt(dwc, &event->depevt);
  2019. }
  2020. switch (event->type.type) {
  2021. case DWC3_EVENT_TYPE_DEV:
  2022. dwc3_gadget_interrupt(dwc, &event->devt);
  2023. break;
  2024. /* REVISIT what to do with Carkit and I2C events ? */
  2025. default:
  2026. dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
  2027. }
  2028. }
  2029. static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
  2030. {
  2031. struct dwc3_event_buffer *evt;
  2032. irqreturn_t ret = IRQ_NONE;
  2033. int left;
  2034. u32 reg;
  2035. evt = dwc->ev_buffs[buf];
  2036. left = evt->count;
  2037. if (!(evt->flags & DWC3_EVENT_PENDING))
  2038. return IRQ_NONE;
  2039. while (left > 0) {
  2040. union dwc3_event event;
  2041. event.raw = *(u32 *) (evt->buf + evt->lpos);
  2042. dwc3_process_event_entry(dwc, &event);
  2043. /*
  2044. * FIXME we wrap around correctly to the next entry as
  2045. * almost all entries are 4 bytes in size. There is one
  2046. * entry which has 12 bytes which is a regular entry
  2047. * followed by 8 bytes data. ATM I don't know how
  2048. * things are organized if we get next to the a
  2049. * boundary so I worry about that once we try to handle
  2050. * that.
  2051. */
  2052. evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
  2053. left -= 4;
  2054. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
  2055. }
  2056. evt->count = 0;
  2057. evt->flags &= ~DWC3_EVENT_PENDING;
  2058. ret = IRQ_HANDLED;
  2059. /* Unmask interrupt */
  2060. reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
  2061. reg &= ~DWC3_GEVNTSIZ_INTMASK;
  2062. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
  2063. return ret;
  2064. }
  2065. static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
  2066. {
  2067. struct dwc3 *dwc = _dwc;
  2068. unsigned long flags;
  2069. irqreturn_t ret = IRQ_NONE;
  2070. int i;
  2071. spin_lock_irqsave(&dwc->lock, flags);
  2072. for (i = 0; i < dwc->num_event_buffers; i++)
  2073. ret |= dwc3_process_event_buf(dwc, i);
  2074. spin_unlock_irqrestore(&dwc->lock, flags);
  2075. return ret;
  2076. }
  2077. static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
  2078. {
  2079. struct dwc3_event_buffer *evt;
  2080. u32 count;
  2081. u32 reg;
  2082. evt = dwc->ev_buffs[buf];
  2083. count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
  2084. count &= DWC3_GEVNTCOUNT_MASK;
  2085. if (!count)
  2086. return IRQ_NONE;
  2087. evt->count = count;
  2088. evt->flags |= DWC3_EVENT_PENDING;
  2089. /* Mask interrupt */
  2090. reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
  2091. reg |= DWC3_GEVNTSIZ_INTMASK;
  2092. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
  2093. return IRQ_WAKE_THREAD;
  2094. }
  2095. static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
  2096. {
  2097. struct dwc3 *dwc = _dwc;
  2098. int i;
  2099. irqreturn_t ret = IRQ_NONE;
  2100. spin_lock(&dwc->lock);
  2101. for (i = 0; i < dwc->num_event_buffers; i++) {
  2102. irqreturn_t status;
  2103. status = dwc3_check_event_buf(dwc, i);
  2104. if (status == IRQ_WAKE_THREAD)
  2105. ret = status;
  2106. }
  2107. spin_unlock(&dwc->lock);
  2108. return ret;
  2109. }
  2110. /**
  2111. * dwc3_gadget_init - Initializes gadget related registers
  2112. * @dwc: pointer to our controller context structure
  2113. *
  2114. * Returns 0 on success otherwise negative errno.
  2115. */
  2116. int dwc3_gadget_init(struct dwc3 *dwc)
  2117. {
  2118. int ret;
  2119. dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
  2120. (unsigned long *)&dwc->ctrl_req_addr);
  2121. if (!dwc->ctrl_req) {
  2122. dev_err(dwc->dev, "failed to allocate ctrl request\n");
  2123. ret = -ENOMEM;
  2124. goto err0;
  2125. }
  2126. dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb) * 2,
  2127. (unsigned long *)&dwc->ep0_trb_addr);
  2128. if (!dwc->ep0_trb) {
  2129. dev_err(dwc->dev, "failed to allocate ep0 trb\n");
  2130. ret = -ENOMEM;
  2131. goto err1;
  2132. }
  2133. dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
  2134. DWC3_EP0_BOUNCE_SIZE);
  2135. if (!dwc->setup_buf) {
  2136. ret = -ENOMEM;
  2137. goto err2;
  2138. }
  2139. dwc->ep0_bounce = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
  2140. (unsigned long *)&dwc->ep0_bounce_addr);
  2141. if (!dwc->ep0_bounce) {
  2142. dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
  2143. ret = -ENOMEM;
  2144. goto err3;
  2145. }
  2146. dwc->gadget.ops = &dwc3_gadget_ops;
  2147. dwc->gadget.max_speed = USB_SPEED_SUPER;
  2148. dwc->gadget.speed = USB_SPEED_UNKNOWN;
  2149. dwc->gadget.name = "dwc3-gadget";
  2150. /*
  2151. * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
  2152. * on ep out.
  2153. */
  2154. dwc->gadget.quirk_ep_out_aligned_size = true;
  2155. /*
  2156. * REVISIT: Here we should clear all pending IRQs to be
  2157. * sure we're starting from a well known location.
  2158. */
  2159. ret = dwc3_gadget_init_endpoints(dwc);
  2160. if (ret)
  2161. goto err4;
  2162. ret = usb_add_gadget_udc((struct device *)dwc->dev, &dwc->gadget);
  2163. if (ret) {
  2164. dev_err(dwc->dev, "failed to register udc\n");
  2165. goto err4;
  2166. }
  2167. return 0;
  2168. err4:
  2169. dwc3_gadget_free_endpoints(dwc);
  2170. dma_free_coherent(dwc->ep0_bounce);
  2171. err3:
  2172. kfree(dwc->setup_buf);
  2173. err2:
  2174. dma_free_coherent(dwc->ep0_trb);
  2175. err1:
  2176. dma_free_coherent(dwc->ctrl_req);
  2177. err0:
  2178. return ret;
  2179. }
  2180. /* -------------------------------------------------------------------------- */
  2181. void dwc3_gadget_exit(struct dwc3 *dwc)
  2182. {
  2183. usb_del_gadget_udc(&dwc->gadget);
  2184. dwc3_gadget_free_endpoints(dwc);
  2185. dma_free_coherent(dwc->ep0_bounce);
  2186. kfree(dwc->setup_buf);
  2187. dma_free_coherent(dwc->ep0_trb);
  2188. dma_free_coherent(dwc->ctrl_req);
  2189. }
  2190. /**
  2191. * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
  2192. * @dwc: struct dwce *
  2193. *
  2194. * Handles ep0 and gadget interrupt
  2195. *
  2196. * Should be called from dwc3 core.
  2197. */
  2198. void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
  2199. {
  2200. int ret = dwc3_interrupt(0, dwc);
  2201. if (ret == IRQ_WAKE_THREAD) {
  2202. int i;
  2203. struct dwc3_event_buffer *evt;
  2204. dwc3_thread_interrupt(0, dwc);
  2205. /* Clean + Invalidate the buffers after touching them */
  2206. for (i = 0; i < dwc->num_event_buffers; i++) {
  2207. evt = dwc->ev_buffs[i];
  2208. dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
  2209. }
  2210. }
  2211. }