ep0.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
  4. *
  5. * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. *
  10. * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported
  11. * to uboot.
  12. *
  13. * commit c00552ebaf : Merge 3.18-rc7 into usb-next
  14. */
  15. #include <common.h>
  16. #include <cpu_func.h>
  17. #include <dm.h>
  18. #include <dm/device_compat.h>
  19. #include <linux/bug.h>
  20. #include <linux/kernel.h>
  21. #include <linux/list.h>
  22. #include <linux/usb/ch9.h>
  23. #include <linux/usb/gadget.h>
  24. #include <linux/usb/composite.h>
  25. #include "core.h"
  26. #include "gadget.h"
  27. #include "io.h"
  28. #include "linux-compat.h"
  29. static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  30. static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  31. struct dwc3_ep *dep, struct dwc3_request *req);
  32. static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  33. {
  34. switch (state) {
  35. case EP0_UNCONNECTED:
  36. return "Unconnected";
  37. case EP0_SETUP_PHASE:
  38. return "Setup Phase";
  39. case EP0_DATA_PHASE:
  40. return "Data Phase";
  41. case EP0_STATUS_PHASE:
  42. return "Status Phase";
  43. default:
  44. return "UNKNOWN";
  45. }
  46. }
  47. static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  48. u32 len, u32 type, unsigned chain)
  49. {
  50. struct dwc3_gadget_ep_cmd_params params;
  51. struct dwc3_trb *trb;
  52. struct dwc3_ep *dep;
  53. int ret;
  54. dep = dwc->eps[epnum];
  55. if (dep->flags & DWC3_EP_BUSY) {
  56. dev_vdbg(dwc->dev, "%s still busy", dep->name);
  57. return 0;
  58. }
  59. trb = &dwc->ep0_trb[dep->free_slot];
  60. if (chain)
  61. dep->free_slot++;
  62. trb->bpl = lower_32_bits(buf_dma);
  63. trb->bph = upper_32_bits(buf_dma);
  64. trb->size = len;
  65. trb->ctrl = type;
  66. trb->ctrl |= (DWC3_TRB_CTRL_HWO
  67. | DWC3_TRB_CTRL_ISP_IMI);
  68. if (chain)
  69. trb->ctrl |= DWC3_TRB_CTRL_CHN;
  70. else
  71. trb->ctrl |= (DWC3_TRB_CTRL_IOC
  72. | DWC3_TRB_CTRL_LST);
  73. dwc3_flush_cache((uintptr_t)buf_dma, len);
  74. dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
  75. if (chain)
  76. return 0;
  77. memset(&params, 0, sizeof(params));
  78. params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  79. params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  80. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
  81. DWC3_DEPCMD_STARTTRANSFER, &params);
  82. if (ret < 0) {
  83. dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name);
  84. return ret;
  85. }
  86. dep->flags |= DWC3_EP_BUSY;
  87. dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
  88. dep->number);
  89. dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  90. return 0;
  91. }
  92. static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
  93. struct dwc3_request *req)
  94. {
  95. struct dwc3 *dwc = dep->dwc;
  96. req->request.actual = 0;
  97. req->request.status = -EINPROGRESS;
  98. req->epnum = dep->number;
  99. list_add_tail(&req->list, &dep->request_list);
  100. /*
  101. * Gadget driver might not be quick enough to queue a request
  102. * before we get a Transfer Not Ready event on this endpoint.
  103. *
  104. * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
  105. * flag is set, it's telling us that as soon as Gadget queues the
  106. * required request, we should kick the transfer here because the
  107. * IRQ we were waiting for is long gone.
  108. */
  109. if (dep->flags & DWC3_EP_PENDING_REQUEST) {
  110. unsigned direction;
  111. direction = !!(dep->flags & DWC3_EP0_DIR_IN);
  112. if (dwc->ep0state != EP0_DATA_PHASE) {
  113. dev_WARN(dwc->dev, "Unexpected pending request\n");
  114. return 0;
  115. }
  116. __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
  117. dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
  118. DWC3_EP0_DIR_IN);
  119. return 0;
  120. }
  121. /*
  122. * In case gadget driver asked us to delay the STATUS phase,
  123. * handle it here.
  124. */
  125. if (dwc->delayed_status) {
  126. unsigned direction;
  127. direction = !dwc->ep0_expect_in;
  128. dwc->delayed_status = false;
  129. usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
  130. if (dwc->ep0state == EP0_STATUS_PHASE)
  131. __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
  132. else
  133. dev_dbg(dwc->dev, "too early for delayed status");
  134. return 0;
  135. }
  136. /*
  137. * Unfortunately we have uncovered a limitation wrt the Data Phase.
  138. *
  139. * Section 9.4 says we can wait for the XferNotReady(DATA) event to
  140. * come before issueing Start Transfer command, but if we do, we will
  141. * miss situations where the host starts another SETUP phase instead of
  142. * the DATA phase. Such cases happen at least on TD.7.6 of the Link
  143. * Layer Compliance Suite.
  144. *
  145. * The problem surfaces due to the fact that in case of back-to-back
  146. * SETUP packets there will be no XferNotReady(DATA) generated and we
  147. * will be stuck waiting for XferNotReady(DATA) forever.
  148. *
  149. * By looking at tables 9-13 and 9-14 of the Databook, we can see that
  150. * it tells us to start Data Phase right away. It also mentions that if
  151. * we receive a SETUP phase instead of the DATA phase, core will issue
  152. * XferComplete for the DATA phase, before actually initiating it in
  153. * the wire, with the TRB's status set to "SETUP_PENDING". Such status
  154. * can only be used to print some debugging logs, as the core expects
  155. * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
  156. * just so it completes right away, without transferring anything and,
  157. * only then, we can go back to the SETUP phase.
  158. *
  159. * Because of this scenario, SNPS decided to change the programming
  160. * model of control transfers and support on-demand transfers only for
  161. * the STATUS phase. To fix the issue we have now, we will always wait
  162. * for gadget driver to queue the DATA phase's struct usb_request, then
  163. * start it right away.
  164. *
  165. * If we're actually in a 2-stage transfer, we will wait for
  166. * XferNotReady(STATUS).
  167. */
  168. if (dwc->three_stage_setup) {
  169. unsigned direction;
  170. direction = dwc->ep0_expect_in;
  171. dwc->ep0state = EP0_DATA_PHASE;
  172. __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
  173. dep->flags &= ~DWC3_EP0_DIR_IN;
  174. }
  175. return 0;
  176. }
  177. int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
  178. gfp_t gfp_flags)
  179. {
  180. struct dwc3_request *req = to_dwc3_request(request);
  181. struct dwc3_ep *dep = to_dwc3_ep(ep);
  182. struct dwc3 *dwc = dep->dwc;
  183. unsigned long flags;
  184. int ret;
  185. spin_lock_irqsave(&dwc->lock, flags);
  186. if (!dep->endpoint.desc) {
  187. dev_dbg(dwc->dev, "trying to queue request %p to disabled %s",
  188. request, dep->name);
  189. ret = -ESHUTDOWN;
  190. goto out;
  191. }
  192. /* we share one TRB for ep0/1 */
  193. if (!list_empty(&dep->request_list)) {
  194. ret = -EBUSY;
  195. goto out;
  196. }
  197. dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'",
  198. request, dep->name, request->length,
  199. dwc3_ep0_state_string(dwc->ep0state));
  200. ret = __dwc3_gadget_ep0_queue(dep, req);
  201. out:
  202. spin_unlock_irqrestore(&dwc->lock, flags);
  203. return ret;
  204. }
  205. static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
  206. {
  207. struct dwc3_ep *dep;
  208. /* reinitialize physical ep1 */
  209. dep = dwc->eps[1];
  210. dep->flags = DWC3_EP_ENABLED;
  211. /* stall is always issued on EP0 */
  212. dep = dwc->eps[0];
  213. __dwc3_gadget_ep_set_halt(dep, 1, false);
  214. dep->flags = DWC3_EP_ENABLED;
  215. dwc->delayed_status = false;
  216. if (!list_empty(&dep->request_list)) {
  217. struct dwc3_request *req;
  218. req = next_request(&dep->request_list);
  219. dwc3_gadget_giveback(dep, req, -ECONNRESET);
  220. }
  221. dwc->ep0state = EP0_SETUP_PHASE;
  222. dwc3_ep0_out_start(dwc);
  223. }
  224. int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
  225. {
  226. struct dwc3_ep *dep = to_dwc3_ep(ep);
  227. struct dwc3 *dwc = dep->dwc;
  228. dwc3_ep0_stall_and_restart(dwc);
  229. return 0;
  230. }
  231. int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
  232. {
  233. unsigned long flags;
  234. int ret;
  235. spin_lock_irqsave(&dwc->lock, flags);
  236. ret = __dwc3_gadget_ep0_set_halt(ep, value);
  237. spin_unlock_irqrestore(&dwc->lock, flags);
  238. return ret;
  239. }
  240. void dwc3_ep0_out_start(struct dwc3 *dwc)
  241. {
  242. int ret;
  243. ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
  244. DWC3_TRBCTL_CONTROL_SETUP, 0);
  245. WARN_ON(ret < 0);
  246. }
  247. static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
  248. {
  249. struct dwc3_ep *dep;
  250. u32 windex = le16_to_cpu(wIndex_le);
  251. u32 epnum;
  252. epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
  253. if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
  254. epnum |= 1;
  255. dep = dwc->eps[epnum];
  256. if (dep->flags & DWC3_EP_ENABLED)
  257. return dep;
  258. return NULL;
  259. }
  260. static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
  261. {
  262. }
  263. /*
  264. * ch 9.4.5
  265. */
  266. static int dwc3_ep0_handle_status(struct dwc3 *dwc,
  267. struct usb_ctrlrequest *ctrl)
  268. {
  269. struct dwc3_ep *dep;
  270. u32 recip;
  271. u32 reg;
  272. u16 usb_status = 0;
  273. __le16 *response_pkt;
  274. recip = ctrl->bRequestType & USB_RECIP_MASK;
  275. switch (recip) {
  276. case USB_RECIP_DEVICE:
  277. /*
  278. * LTM will be set once we know how to set this in HW.
  279. */
  280. usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
  281. if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
  282. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  283. if (reg & DWC3_DCTL_INITU1ENA)
  284. usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
  285. if (reg & DWC3_DCTL_INITU2ENA)
  286. usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
  287. }
  288. break;
  289. case USB_RECIP_INTERFACE:
  290. /*
  291. * Function Remote Wake Capable D0
  292. * Function Remote Wakeup D1
  293. */
  294. break;
  295. case USB_RECIP_ENDPOINT:
  296. dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
  297. if (!dep)
  298. return -EINVAL;
  299. if (dep->flags & DWC3_EP_STALL)
  300. usb_status = 1 << USB_ENDPOINT_HALT;
  301. break;
  302. default:
  303. return -EINVAL;
  304. }
  305. response_pkt = (__le16 *) dwc->setup_buf;
  306. *response_pkt = cpu_to_le16(usb_status);
  307. dep = dwc->eps[0];
  308. dwc->ep0_usb_req.dep = dep;
  309. dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
  310. dwc->ep0_usb_req.request.buf = dwc->setup_buf;
  311. dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
  312. return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
  313. }
  314. static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
  315. struct usb_ctrlrequest *ctrl, int set)
  316. {
  317. struct dwc3_ep *dep;
  318. u32 recip;
  319. u32 wValue;
  320. u32 wIndex;
  321. u32 reg;
  322. int ret;
  323. enum usb_device_state state;
  324. wValue = le16_to_cpu(ctrl->wValue);
  325. wIndex = le16_to_cpu(ctrl->wIndex);
  326. recip = ctrl->bRequestType & USB_RECIP_MASK;
  327. state = dwc->gadget.state;
  328. switch (recip) {
  329. case USB_RECIP_DEVICE:
  330. switch (wValue) {
  331. case USB_DEVICE_REMOTE_WAKEUP:
  332. break;
  333. /*
  334. * 9.4.1 says only only for SS, in AddressState only for
  335. * default control pipe
  336. */
  337. case USB_DEVICE_U1_ENABLE:
  338. if (state != USB_STATE_CONFIGURED)
  339. return -EINVAL;
  340. if (dwc->speed != DWC3_DSTS_SUPERSPEED)
  341. return -EINVAL;
  342. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  343. if (set)
  344. reg |= DWC3_DCTL_INITU1ENA;
  345. else
  346. reg &= ~DWC3_DCTL_INITU1ENA;
  347. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  348. break;
  349. case USB_DEVICE_U2_ENABLE:
  350. if (state != USB_STATE_CONFIGURED)
  351. return -EINVAL;
  352. if (dwc->speed != DWC3_DSTS_SUPERSPEED)
  353. return -EINVAL;
  354. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  355. if (set)
  356. reg |= DWC3_DCTL_INITU2ENA;
  357. else
  358. reg &= ~DWC3_DCTL_INITU2ENA;
  359. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  360. break;
  361. case USB_DEVICE_LTM_ENABLE:
  362. return -EINVAL;
  363. case USB_DEVICE_TEST_MODE:
  364. if ((wIndex & 0xff) != 0)
  365. return -EINVAL;
  366. if (!set)
  367. return -EINVAL;
  368. dwc->test_mode_nr = wIndex >> 8;
  369. dwc->test_mode = true;
  370. break;
  371. default:
  372. return -EINVAL;
  373. }
  374. break;
  375. case USB_RECIP_INTERFACE:
  376. switch (wValue) {
  377. case USB_INTRF_FUNC_SUSPEND:
  378. if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
  379. /* XXX enable Low power suspend */
  380. ;
  381. if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
  382. /* XXX enable remote wakeup */
  383. ;
  384. break;
  385. default:
  386. return -EINVAL;
  387. }
  388. break;
  389. case USB_RECIP_ENDPOINT:
  390. switch (wValue) {
  391. case USB_ENDPOINT_HALT:
  392. dep = dwc3_wIndex_to_dep(dwc, wIndex);
  393. if (!dep)
  394. return -EINVAL;
  395. if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
  396. break;
  397. ret = __dwc3_gadget_ep_set_halt(dep, set, true);
  398. if (ret)
  399. return -EINVAL;
  400. break;
  401. default:
  402. return -EINVAL;
  403. }
  404. break;
  405. default:
  406. return -EINVAL;
  407. }
  408. return 0;
  409. }
  410. static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  411. {
  412. enum usb_device_state state = dwc->gadget.state;
  413. u32 addr;
  414. u32 reg;
  415. addr = le16_to_cpu(ctrl->wValue);
  416. if (addr > 127) {
  417. dev_dbg(dwc->dev, "invalid device address %d", addr);
  418. return -EINVAL;
  419. }
  420. if (state == USB_STATE_CONFIGURED) {
  421. dev_dbg(dwc->dev, "trying to set address when configured");
  422. return -EINVAL;
  423. }
  424. reg = dwc3_readl(dwc->regs, DWC3_DCFG);
  425. reg &= ~(DWC3_DCFG_DEVADDR_MASK);
  426. reg |= DWC3_DCFG_DEVADDR(addr);
  427. dwc3_writel(dwc->regs, DWC3_DCFG, reg);
  428. if (addr)
  429. usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
  430. else
  431. usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
  432. return 0;
  433. }
  434. static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  435. {
  436. int ret;
  437. spin_unlock(&dwc->lock);
  438. ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
  439. spin_lock(&dwc->lock);
  440. return ret;
  441. }
  442. static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  443. {
  444. enum usb_device_state state = dwc->gadget.state;
  445. u32 cfg;
  446. int ret;
  447. u32 reg;
  448. dwc->start_config_issued = false;
  449. cfg = le16_to_cpu(ctrl->wValue);
  450. switch (state) {
  451. case USB_STATE_DEFAULT:
  452. return -EINVAL;
  453. case USB_STATE_ADDRESS:
  454. ret = dwc3_ep0_delegate_req(dwc, ctrl);
  455. /* if the cfg matches and the cfg is non zero */
  456. if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
  457. /*
  458. * only change state if set_config has already
  459. * been processed. If gadget driver returns
  460. * USB_GADGET_DELAYED_STATUS, we will wait
  461. * to change the state on the next usb_ep_queue()
  462. */
  463. if (ret == 0)
  464. usb_gadget_set_state(&dwc->gadget,
  465. USB_STATE_CONFIGURED);
  466. /*
  467. * Enable transition to U1/U2 state when
  468. * nothing is pending from application.
  469. */
  470. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  471. reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
  472. dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  473. dwc->resize_fifos = true;
  474. dev_dbg(dwc->dev, "resize FIFOs flag SET");
  475. }
  476. break;
  477. case USB_STATE_CONFIGURED:
  478. ret = dwc3_ep0_delegate_req(dwc, ctrl);
  479. if (!cfg && !ret)
  480. usb_gadget_set_state(&dwc->gadget,
  481. USB_STATE_ADDRESS);
  482. break;
  483. default:
  484. ret = -EINVAL;
  485. }
  486. return ret;
  487. }
  488. static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
  489. {
  490. struct dwc3_ep *dep = to_dwc3_ep(ep);
  491. struct dwc3 *dwc = dep->dwc;
  492. u32 param = 0;
  493. u32 reg;
  494. struct timing {
  495. u8 u1sel;
  496. u8 u1pel;
  497. u16 u2sel;
  498. u16 u2pel;
  499. } __packed timing;
  500. int ret;
  501. memcpy(&timing, req->buf, sizeof(timing));
  502. dwc->u1sel = timing.u1sel;
  503. dwc->u1pel = timing.u1pel;
  504. dwc->u2sel = le16_to_cpu(timing.u2sel);
  505. dwc->u2pel = le16_to_cpu(timing.u2pel);
  506. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  507. if (reg & DWC3_DCTL_INITU2ENA)
  508. param = dwc->u2pel;
  509. if (reg & DWC3_DCTL_INITU1ENA)
  510. param = dwc->u1pel;
  511. /*
  512. * According to Synopsys Databook, if parameter is
  513. * greater than 125, a value of zero should be
  514. * programmed in the register.
  515. */
  516. if (param > 125)
  517. param = 0;
  518. /* now that we have the time, issue DGCMD Set Sel */
  519. ret = dwc3_send_gadget_generic_command(dwc,
  520. DWC3_DGCMD_SET_PERIODIC_PAR, param);
  521. WARN_ON(ret < 0);
  522. }
  523. static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  524. {
  525. struct dwc3_ep *dep;
  526. enum usb_device_state state = dwc->gadget.state;
  527. u16 wLength;
  528. if (state == USB_STATE_DEFAULT)
  529. return -EINVAL;
  530. wLength = le16_to_cpu(ctrl->wLength);
  531. if (wLength != 6) {
  532. dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
  533. wLength);
  534. return -EINVAL;
  535. }
  536. /*
  537. * To handle Set SEL we need to receive 6 bytes from Host. So let's
  538. * queue a usb_request for 6 bytes.
  539. *
  540. * Remember, though, this controller can't handle non-wMaxPacketSize
  541. * aligned transfers on the OUT direction, so we queue a request for
  542. * wMaxPacketSize instead.
  543. */
  544. dep = dwc->eps[0];
  545. dwc->ep0_usb_req.dep = dep;
  546. dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
  547. dwc->ep0_usb_req.request.buf = dwc->setup_buf;
  548. dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
  549. return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
  550. }
  551. static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  552. {
  553. u16 wLength;
  554. u16 wValue;
  555. u16 wIndex;
  556. wValue = le16_to_cpu(ctrl->wValue);
  557. wLength = le16_to_cpu(ctrl->wLength);
  558. wIndex = le16_to_cpu(ctrl->wIndex);
  559. if (wIndex || wLength)
  560. return -EINVAL;
  561. /*
  562. * REVISIT It's unclear from Databook what to do with this
  563. * value. For now, just cache it.
  564. */
  565. dwc->isoch_delay = wValue;
  566. return 0;
  567. }
  568. static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
  569. {
  570. int ret;
  571. switch (ctrl->bRequest) {
  572. case USB_REQ_GET_STATUS:
  573. dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS");
  574. ret = dwc3_ep0_handle_status(dwc, ctrl);
  575. break;
  576. case USB_REQ_CLEAR_FEATURE:
  577. dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE");
  578. ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
  579. break;
  580. case USB_REQ_SET_FEATURE:
  581. dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE");
  582. ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
  583. break;
  584. case USB_REQ_SET_ADDRESS:
  585. dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS");
  586. ret = dwc3_ep0_set_address(dwc, ctrl);
  587. break;
  588. case USB_REQ_SET_CONFIGURATION:
  589. dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION");
  590. ret = dwc3_ep0_set_config(dwc, ctrl);
  591. break;
  592. case USB_REQ_SET_SEL:
  593. dev_vdbg(dwc->dev, "USB_REQ_SET_SEL");
  594. ret = dwc3_ep0_set_sel(dwc, ctrl);
  595. break;
  596. case USB_REQ_SET_ISOCH_DELAY:
  597. dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY");
  598. ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
  599. break;
  600. default:
  601. dev_vdbg(dwc->dev, "Forwarding to gadget driver");
  602. ret = dwc3_ep0_delegate_req(dwc, ctrl);
  603. break;
  604. }
  605. return ret;
  606. }
  607. static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
  608. const struct dwc3_event_depevt *event)
  609. {
  610. struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
  611. int ret = -EINVAL;
  612. u32 len;
  613. if (!dwc->gadget_driver)
  614. goto out;
  615. len = le16_to_cpu(ctrl->wLength);
  616. if (!len) {
  617. dwc->three_stage_setup = false;
  618. dwc->ep0_expect_in = false;
  619. dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
  620. } else {
  621. dwc->three_stage_setup = true;
  622. dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
  623. dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
  624. }
  625. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
  626. ret = dwc3_ep0_std_request(dwc, ctrl);
  627. else
  628. ret = dwc3_ep0_delegate_req(dwc, ctrl);
  629. if (ret == USB_GADGET_DELAYED_STATUS)
  630. dwc->delayed_status = true;
  631. out:
  632. if (ret < 0)
  633. dwc3_ep0_stall_and_restart(dwc);
  634. }
  635. static void dwc3_ep0_complete_data(struct dwc3 *dwc,
  636. const struct dwc3_event_depevt *event)
  637. {
  638. struct dwc3_request *r = NULL;
  639. struct usb_request *ur;
  640. struct dwc3_trb *trb;
  641. struct dwc3_ep *ep0;
  642. unsigned transfer_size = 0;
  643. unsigned maxp;
  644. void *buf;
  645. u32 transferred = 0;
  646. u32 status;
  647. u32 length;
  648. u8 epnum;
  649. epnum = event->endpoint_number;
  650. ep0 = dwc->eps[0];
  651. dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
  652. trb = dwc->ep0_trb;
  653. r = next_request(&ep0->request_list);
  654. if (!r)
  655. return;
  656. dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
  657. status = DWC3_TRB_SIZE_TRBSTS(trb->size);
  658. if (status == DWC3_TRBSTS_SETUP_PENDING) {
  659. dev_dbg(dwc->dev, "Setup Pending received");
  660. if (r)
  661. dwc3_gadget_giveback(ep0, r, -ECONNRESET);
  662. return;
  663. }
  664. ur = &r->request;
  665. buf = ur->buf;
  666. length = trb->size & DWC3_TRB_SIZE_MASK;
  667. maxp = ep0->endpoint.maxpacket;
  668. if (dwc->ep0_bounced) {
  669. /*
  670. * Handle the first TRB before handling the bounce buffer if
  671. * the request length is greater than the bounce buffer size.
  672. */
  673. if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
  674. transfer_size = (ur->length / maxp) * maxp;
  675. transferred = transfer_size - length;
  676. buf = (u8 *)buf + transferred;
  677. ur->actual += transferred;
  678. trb++;
  679. dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
  680. length = trb->size & DWC3_TRB_SIZE_MASK;
  681. ep0->free_slot = 0;
  682. }
  683. transfer_size = roundup((ur->length - transfer_size),
  684. maxp);
  685. transferred = min_t(u32, ur->length - transferred,
  686. transfer_size - length);
  687. dwc3_flush_cache((uintptr_t)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
  688. memcpy(buf, dwc->ep0_bounce, transferred);
  689. } else {
  690. transferred = ur->length - length;
  691. }
  692. ur->actual += transferred;
  693. if ((epnum & 1) && ur->actual < ur->length) {
  694. /* for some reason we did not get everything out */
  695. dwc3_ep0_stall_and_restart(dwc);
  696. } else {
  697. dwc3_gadget_giveback(ep0, r, 0);
  698. if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
  699. ur->length && ur->zero) {
  700. int ret;
  701. dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  702. ret = dwc3_ep0_start_trans(dwc, epnum,
  703. dwc->ctrl_req_addr, 0,
  704. DWC3_TRBCTL_CONTROL_DATA, 0);
  705. WARN_ON(ret < 0);
  706. }
  707. }
  708. }
  709. static void dwc3_ep0_complete_status(struct dwc3 *dwc,
  710. const struct dwc3_event_depevt *event)
  711. {
  712. struct dwc3_request *r;
  713. struct dwc3_ep *dep;
  714. struct dwc3_trb *trb;
  715. u32 status;
  716. dep = dwc->eps[0];
  717. trb = dwc->ep0_trb;
  718. if (!list_empty(&dep->request_list)) {
  719. r = next_request(&dep->request_list);
  720. dwc3_gadget_giveback(dep, r, 0);
  721. }
  722. if (dwc->test_mode) {
  723. int ret;
  724. ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
  725. if (ret < 0) {
  726. dev_dbg(dwc->dev, "Invalid Test #%d",
  727. dwc->test_mode_nr);
  728. dwc3_ep0_stall_and_restart(dwc);
  729. return;
  730. }
  731. }
  732. status = DWC3_TRB_SIZE_TRBSTS(trb->size);
  733. if (status == DWC3_TRBSTS_SETUP_PENDING)
  734. dev_dbg(dwc->dev, "Setup Pending received");
  735. dwc->ep0state = EP0_SETUP_PHASE;
  736. dwc3_ep0_out_start(dwc);
  737. }
  738. static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
  739. const struct dwc3_event_depevt *event)
  740. {
  741. struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
  742. dep->flags &= ~DWC3_EP_BUSY;
  743. dep->resource_index = 0;
  744. dwc->setup_packet_pending = false;
  745. switch (dwc->ep0state) {
  746. case EP0_SETUP_PHASE:
  747. dev_vdbg(dwc->dev, "Setup Phase");
  748. dwc3_ep0_inspect_setup(dwc, event);
  749. break;
  750. case EP0_DATA_PHASE:
  751. dev_vdbg(dwc->dev, "Data Phase");
  752. dwc3_ep0_complete_data(dwc, event);
  753. break;
  754. case EP0_STATUS_PHASE:
  755. dev_vdbg(dwc->dev, "Status Phase");
  756. dwc3_ep0_complete_status(dwc, event);
  757. break;
  758. default:
  759. WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
  760. }
  761. }
  762. static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  763. struct dwc3_ep *dep, struct dwc3_request *req)
  764. {
  765. int ret;
  766. req->direction = !!dep->number;
  767. if (req->request.length == 0) {
  768. ret = dwc3_ep0_start_trans(dwc, dep->number,
  769. dwc->ctrl_req_addr, 0,
  770. DWC3_TRBCTL_CONTROL_DATA, 0);
  771. } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
  772. (dep->number == 0)) {
  773. u32 transfer_size = 0;
  774. u32 maxpacket;
  775. ret = usb_gadget_map_request(&dwc->gadget, &req->request,
  776. dep->number);
  777. if (ret) {
  778. dev_dbg(dwc->dev, "failed to map request\n");
  779. return;
  780. }
  781. maxpacket = dep->endpoint.maxpacket;
  782. if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
  783. transfer_size = (req->request.length / maxpacket) *
  784. maxpacket;
  785. ret = dwc3_ep0_start_trans(dwc, dep->number,
  786. req->request.dma,
  787. transfer_size,
  788. DWC3_TRBCTL_CONTROL_DATA, 1);
  789. }
  790. transfer_size = roundup((req->request.length - transfer_size),
  791. maxpacket);
  792. dwc->ep0_bounced = true;
  793. /*
  794. * REVISIT in case request length is bigger than
  795. * DWC3_EP0_BOUNCE_SIZE we will need two chained
  796. * TRBs to handle the transfer.
  797. */
  798. ret = dwc3_ep0_start_trans(dwc, dep->number,
  799. dwc->ep0_bounce_addr, transfer_size,
  800. DWC3_TRBCTL_CONTROL_DATA, 0);
  801. } else {
  802. ret = usb_gadget_map_request(&dwc->gadget, &req->request,
  803. dep->number);
  804. if (ret) {
  805. dev_dbg(dwc->dev, "failed to map request\n");
  806. return;
  807. }
  808. ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
  809. req->request.length,
  810. DWC3_TRBCTL_CONTROL_DATA, 0);
  811. }
  812. WARN_ON(ret < 0);
  813. }
  814. static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
  815. {
  816. struct dwc3 *dwc = dep->dwc;
  817. u32 type;
  818. type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
  819. : DWC3_TRBCTL_CONTROL_STATUS2;
  820. return dwc3_ep0_start_trans(dwc, dep->number,
  821. dwc->ctrl_req_addr, 0, type, 0);
  822. }
  823. static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
  824. {
  825. if (dwc->resize_fifos) {
  826. dev_dbg(dwc->dev, "Resizing FIFOs");
  827. dwc3_gadget_resize_tx_fifos(dwc);
  828. dwc->resize_fifos = 0;
  829. }
  830. WARN_ON(dwc3_ep0_start_control_status(dep));
  831. }
  832. static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
  833. const struct dwc3_event_depevt *event)
  834. {
  835. struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
  836. __dwc3_ep0_do_control_status(dwc, dep);
  837. }
  838. static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
  839. {
  840. struct dwc3_gadget_ep_cmd_params params;
  841. u32 cmd;
  842. int ret;
  843. if (!dep->resource_index)
  844. return;
  845. cmd = DWC3_DEPCMD_ENDTRANSFER;
  846. cmd |= DWC3_DEPCMD_CMDIOC;
  847. cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
  848. memset(&params, 0, sizeof(params));
  849. ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
  850. WARN_ON_ONCE(ret);
  851. dep->resource_index = 0;
  852. }
  853. static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
  854. const struct dwc3_event_depevt *event)
  855. {
  856. dwc->setup_packet_pending = true;
  857. switch (event->status) {
  858. case DEPEVT_STATUS_CONTROL_DATA:
  859. dev_vdbg(dwc->dev, "Control Data");
  860. /*
  861. * We already have a DATA transfer in the controller's cache,
  862. * if we receive a XferNotReady(DATA) we will ignore it, unless
  863. * it's for the wrong direction.
  864. *
  865. * In that case, we must issue END_TRANSFER command to the Data
  866. * Phase we already have started and issue SetStall on the
  867. * control endpoint.
  868. */
  869. if (dwc->ep0_expect_in != event->endpoint_number) {
  870. struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
  871. dev_vdbg(dwc->dev, "Wrong direction for Data phase");
  872. dwc3_ep0_end_control_data(dwc, dep);
  873. dwc3_ep0_stall_and_restart(dwc);
  874. return;
  875. }
  876. break;
  877. case DEPEVT_STATUS_CONTROL_STATUS:
  878. if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
  879. return;
  880. dev_vdbg(dwc->dev, "Control Status");
  881. dwc->ep0state = EP0_STATUS_PHASE;
  882. if (dwc->delayed_status) {
  883. WARN_ON_ONCE(event->endpoint_number != 1);
  884. dev_vdbg(dwc->dev, "Delayed Status");
  885. return;
  886. }
  887. dwc3_ep0_do_control_status(dwc, event);
  888. }
  889. }
  890. void dwc3_ep0_interrupt(struct dwc3 *dwc,
  891. const struct dwc3_event_depevt *event)
  892. {
  893. u8 epnum = event->endpoint_number;
  894. dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'",
  895. dwc3_ep_event_string(event->endpoint_event),
  896. epnum >> 1, (epnum & 1) ? "in" : "out",
  897. dwc3_ep0_state_string(dwc->ep0state));
  898. switch (event->endpoint_event) {
  899. case DWC3_DEPEVT_XFERCOMPLETE:
  900. dwc3_ep0_xfer_complete(dwc, event);
  901. break;
  902. case DWC3_DEPEVT_XFERNOTREADY:
  903. dwc3_ep0_xfernotready(dwc, event);
  904. break;
  905. case DWC3_DEPEVT_XFERINPROGRESS:
  906. case DWC3_DEPEVT_RXTXFIFOEVT:
  907. case DWC3_DEPEVT_STREAMEVT:
  908. case DWC3_DEPEVT_EPCMDCMPLT:
  909. break;
  910. }
  911. }