dwc3-omap.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * dwc3-omap.c - OMAP Specific Glue layer
  4. *
  5. * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. *
  10. * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/dwc3-omap.c) and ported
  11. * to uboot.
  12. *
  13. * commit 7ee2566ff5 : usb: dwc3: dwc3-omap: get rid of ->prepare()/->complete()
  14. */
  15. #include <common.h>
  16. #include <malloc.h>
  17. #include <asm/io.h>
  18. #include <dm.h>
  19. #include <dwc3-omap-uboot.h>
  20. #include <dm/device_compat.h>
  21. #include <dm/devres.h>
  22. #include <linux/usb/dwc3-omap.h>
  23. #include <linux/ioport.h>
  24. #include <linux/usb/otg.h>
  25. #include <linux/compat.h>
  26. #include "linux-compat.h"
  27. /*
  28. * All these registers belong to OMAP's Wrapper around the
  29. * DesignWare USB3 Core.
  30. */
  31. #define USBOTGSS_REVISION 0x0000
  32. #define USBOTGSS_SYSCONFIG 0x0010
  33. #define USBOTGSS_IRQ_EOI 0x0020
  34. #define USBOTGSS_EOI_OFFSET 0x0008
  35. #define USBOTGSS_IRQSTATUS_RAW_0 0x0024
  36. #define USBOTGSS_IRQSTATUS_0 0x0028
  37. #define USBOTGSS_IRQENABLE_SET_0 0x002c
  38. #define USBOTGSS_IRQENABLE_CLR_0 0x0030
  39. #define USBOTGSS_IRQ0_OFFSET 0x0004
  40. #define USBOTGSS_IRQSTATUS_RAW_1 0x0030
  41. #define USBOTGSS_IRQSTATUS_1 0x0034
  42. #define USBOTGSS_IRQENABLE_SET_1 0x0038
  43. #define USBOTGSS_IRQENABLE_CLR_1 0x003c
  44. #define USBOTGSS_IRQSTATUS_RAW_2 0x0040
  45. #define USBOTGSS_IRQSTATUS_2 0x0044
  46. #define USBOTGSS_IRQENABLE_SET_2 0x0048
  47. #define USBOTGSS_IRQENABLE_CLR_2 0x004c
  48. #define USBOTGSS_IRQSTATUS_RAW_3 0x0050
  49. #define USBOTGSS_IRQSTATUS_3 0x0054
  50. #define USBOTGSS_IRQENABLE_SET_3 0x0058
  51. #define USBOTGSS_IRQENABLE_CLR_3 0x005c
  52. #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
  53. #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
  54. #define USBOTGSS_IRQSTATUS_MISC 0x0038
  55. #define USBOTGSS_IRQENABLE_SET_MISC 0x003c
  56. #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
  57. #define USBOTGSS_IRQMISC_OFFSET 0x03fc
  58. #define USBOTGSS_UTMI_OTG_CTRL 0x0080
  59. #define USBOTGSS_UTMI_OTG_STATUS 0x0084
  60. #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
  61. #define USBOTGSS_TXFIFO_DEPTH 0x0508
  62. #define USBOTGSS_RXFIFO_DEPTH 0x050c
  63. #define USBOTGSS_MMRAM_OFFSET 0x0100
  64. #define USBOTGSS_FLADJ 0x0104
  65. #define USBOTGSS_DEBUG_CFG 0x0108
  66. #define USBOTGSS_DEBUG_DATA 0x010c
  67. #define USBOTGSS_DEV_EBC_EN 0x0110
  68. #define USBOTGSS_DEBUG_OFFSET 0x0600
  69. /* SYSCONFIG REGISTER */
  70. #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
  71. /* IRQ_EOI REGISTER */
  72. #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
  73. /* IRQS0 BITS */
  74. #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
  75. /* IRQMISC BITS */
  76. #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17)
  77. #define USBOTGSS_IRQMISC_OEVT (1 << 16)
  78. #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13)
  79. #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12)
  80. #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11)
  81. #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8)
  82. #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5)
  83. #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4)
  84. #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3)
  85. #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0)
  86. #define USBOTGSS_INTERRUPTS (USBOTGSS_IRQMISC_OEVT | \
  87. USBOTGSS_IRQMISC_DRVVBUS_RISE | \
  88. USBOTGSS_IRQMISC_CHRGVBUS_RISE | \
  89. USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | \
  90. USBOTGSS_IRQMISC_IDPULLUP_RISE | \
  91. USBOTGSS_IRQMISC_DRVVBUS_FALL | \
  92. USBOTGSS_IRQMISC_CHRGVBUS_FALL | \
  93. USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | \
  94. USBOTGSS_IRQMISC_IDPULLUP_FALL)
  95. /* UTMI_OTG_CTRL REGISTER */
  96. #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
  97. #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
  98. #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
  99. #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
  100. /* UTMI_OTG_STATUS REGISTER */
  101. #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
  102. #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
  103. #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
  104. #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
  105. #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
  106. #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
  107. #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
  108. struct dwc3_omap {
  109. struct device *dev;
  110. void __iomem *base;
  111. u32 utmi_otg_status;
  112. u32 utmi_otg_offset;
  113. u32 irqmisc_offset;
  114. u32 irq_eoi_offset;
  115. u32 debug_offset;
  116. u32 irq0_offset;
  117. u32 dma_status:1;
  118. struct list_head list;
  119. u32 index;
  120. };
  121. static LIST_HEAD(dwc3_omap_list);
  122. static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
  123. {
  124. return readl(base + offset);
  125. }
  126. static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
  127. {
  128. writel(value, base + offset);
  129. }
  130. static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
  131. {
  132. return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
  133. omap->utmi_otg_offset);
  134. }
  135. static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
  136. {
  137. dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
  138. omap->utmi_otg_offset, value);
  139. }
  140. static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
  141. {
  142. return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
  143. omap->irq0_offset);
  144. }
  145. static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
  146. {
  147. dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
  148. omap->irq0_offset, value);
  149. }
  150. static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
  151. {
  152. return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
  153. omap->irqmisc_offset);
  154. }
  155. static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
  156. {
  157. dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
  158. omap->irqmisc_offset, value);
  159. }
  160. static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
  161. {
  162. dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
  163. omap->irqmisc_offset, value);
  164. }
  165. static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
  166. {
  167. dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
  168. omap->irq0_offset, value);
  169. }
  170. static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
  171. {
  172. dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
  173. omap->irqmisc_offset, value);
  174. }
  175. static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
  176. {
  177. dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
  178. omap->irq0_offset, value);
  179. }
  180. static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
  181. enum omap_dwc3_vbus_id_status status)
  182. {
  183. u32 val;
  184. switch (status) {
  185. case OMAP_DWC3_ID_GROUND:
  186. dev_dbg(omap->dev, "ID GND\n");
  187. val = dwc3_omap_read_utmi_status(omap);
  188. val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
  189. | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
  190. | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
  191. val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
  192. | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
  193. dwc3_omap_write_utmi_status(omap, val);
  194. break;
  195. case OMAP_DWC3_VBUS_VALID:
  196. dev_dbg(omap->dev, "VBUS Connect\n");
  197. val = dwc3_omap_read_utmi_status(omap);
  198. val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
  199. val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
  200. | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
  201. | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
  202. | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
  203. dwc3_omap_write_utmi_status(omap, val);
  204. break;
  205. case OMAP_DWC3_ID_FLOAT:
  206. case OMAP_DWC3_VBUS_OFF:
  207. dev_dbg(omap->dev, "VBUS Disconnect\n");
  208. val = dwc3_omap_read_utmi_status(omap);
  209. val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
  210. | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
  211. | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
  212. val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
  213. | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
  214. dwc3_omap_write_utmi_status(omap, val);
  215. break;
  216. default:
  217. dev_dbg(omap->dev, "invalid state\n");
  218. }
  219. }
  220. static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
  221. {
  222. struct dwc3_omap *omap = _omap;
  223. u32 reg;
  224. reg = dwc3_omap_read_irqmisc_status(omap);
  225. if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
  226. dev_dbg(omap->dev, "DMA Disable was Cleared\n");
  227. omap->dma_status = false;
  228. }
  229. if (reg & USBOTGSS_IRQMISC_OEVT)
  230. dev_dbg(omap->dev, "OTG Event\n");
  231. if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
  232. dev_dbg(omap->dev, "DRVVBUS Rise\n");
  233. if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
  234. dev_dbg(omap->dev, "CHRGVBUS Rise\n");
  235. if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
  236. dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
  237. if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
  238. dev_dbg(omap->dev, "IDPULLUP Rise\n");
  239. if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
  240. dev_dbg(omap->dev, "DRVVBUS Fall\n");
  241. if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
  242. dev_dbg(omap->dev, "CHRGVBUS Fall\n");
  243. if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
  244. dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
  245. if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
  246. dev_dbg(omap->dev, "IDPULLUP Fall\n");
  247. dwc3_omap_write_irqmisc_status(omap, reg);
  248. reg = dwc3_omap_read_irq0_status(omap);
  249. dwc3_omap_write_irq0_status(omap, reg);
  250. return IRQ_HANDLED;
  251. }
  252. static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
  253. {
  254. /* enable all IRQs */
  255. dwc3_omap_write_irq0_set(omap, USBOTGSS_IRQO_COREIRQ_ST);
  256. dwc3_omap_write_irqmisc_set(omap, USBOTGSS_INTERRUPTS);
  257. }
  258. static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
  259. {
  260. /* disable all IRQs */
  261. dwc3_omap_write_irq0_clr(omap, USBOTGSS_IRQO_COREIRQ_ST);
  262. dwc3_omap_write_irqmisc_clr(omap, USBOTGSS_INTERRUPTS);
  263. }
  264. static void dwc3_omap_map_offset(struct dwc3_omap *omap)
  265. {
  266. /*
  267. * Differentiate between OMAP5 and AM437x.
  268. *
  269. * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
  270. * though there are changes in wrapper register offsets.
  271. *
  272. * Using dt compatible to differentiate AM437x.
  273. */
  274. #ifdef CONFIG_AM43XX
  275. omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
  276. omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
  277. omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
  278. omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
  279. omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
  280. #endif
  281. }
  282. static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap, int utmi_mode)
  283. {
  284. u32 reg;
  285. reg = dwc3_omap_read_utmi_status(omap);
  286. switch (utmi_mode) {
  287. case DWC3_OMAP_UTMI_MODE_SW:
  288. reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
  289. break;
  290. case DWC3_OMAP_UTMI_MODE_HW:
  291. reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
  292. break;
  293. default:
  294. dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
  295. }
  296. dwc3_omap_write_utmi_status(omap, reg);
  297. }
  298. /**
  299. * dwc3_omap_uboot_init - dwc3 omap uboot initialization code
  300. * @dev: struct dwc3_omap_device containing initialization data
  301. *
  302. * Entry point for dwc3 omap driver (equivalent to dwc3_omap_probe in linux
  303. * kernel driver). Pointer to dwc3_omap_device should be passed containing
  304. * base address and other initialization data. Returns '0' on success and
  305. * a negative value on failure.
  306. *
  307. * Generally called from board_usb_init() implemented in board file.
  308. */
  309. int dwc3_omap_uboot_init(struct dwc3_omap_device *omap_dev)
  310. {
  311. u32 reg;
  312. struct device *dev = NULL;
  313. struct dwc3_omap *omap;
  314. omap = devm_kzalloc((struct udevice *)dev, sizeof(*omap), GFP_KERNEL);
  315. if (!omap)
  316. return -ENOMEM;
  317. omap->base = omap_dev->base;
  318. omap->index = omap_dev->index;
  319. dwc3_omap_map_offset(omap);
  320. dwc3_omap_set_utmi_mode(omap, omap_dev->utmi_mode);
  321. /* check the DMA Status */
  322. reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
  323. omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
  324. dwc3_omap_set_mailbox(omap, omap_dev->vbus_id_status);
  325. dwc3_omap_enable_irqs(omap);
  326. list_add_tail(&omap->list, &dwc3_omap_list);
  327. return 0;
  328. }
  329. /**
  330. * dwc3_omap_uboot_exit - dwc3 omap uboot cleanup code
  331. * @index: index of this controller
  332. *
  333. * Performs cleanup of memory allocated in dwc3_omap_uboot_init
  334. * (equivalent to dwc3_omap_remove in linux). index of _this_ controller
  335. * should be passed and should match with the index passed in
  336. * dwc3_omap_device during init.
  337. *
  338. * Generally called from board file.
  339. */
  340. void dwc3_omap_uboot_exit(int index)
  341. {
  342. struct dwc3_omap *omap = NULL;
  343. list_for_each_entry(omap, &dwc3_omap_list, list) {
  344. if (omap->index != index)
  345. continue;
  346. dwc3_omap_disable_irqs(omap);
  347. list_del(&omap->list);
  348. kfree(omap);
  349. break;
  350. }
  351. }
  352. /**
  353. * dwc3_omap_uboot_interrupt_status - check the status of interrupt
  354. * @index: index of this controller
  355. *
  356. * Checks the status of interrupts and returns true if an interrupt
  357. * is detected or false otherwise.
  358. *
  359. * Generally called from board file.
  360. */
  361. int dwc3_omap_uboot_interrupt_status(int index)
  362. {
  363. struct dwc3_omap *omap = NULL;
  364. list_for_each_entry(omap, &dwc3_omap_list, list)
  365. if (omap->index == index)
  366. return dwc3_omap_interrupt(-1, omap);
  367. return 0;
  368. }
  369. MODULE_ALIAS("platform:omap-dwc3");
  370. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  371. MODULE_LICENSE("GPL v2");
  372. MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");