dwc3-meson-gxl.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Amlogic GXL DWC3 Glue layer
  4. *
  5. * Copyright (C) 2019 BayLibre, SAS
  6. * Author: Neil Armstrong <narmstrong@baylibre.com>
  7. */
  8. #define DEBUG
  9. #include <common.h>
  10. #include <asm-generic/io.h>
  11. #include <dm.h>
  12. #include <dm/device-internal.h>
  13. #include <dm/lists.h>
  14. #include <dwc3-uboot.h>
  15. #include <generic-phy.h>
  16. #include <linux/usb/ch9.h>
  17. #include <linux/usb/gadget.h>
  18. #include <malloc.h>
  19. #include <regmap.h>
  20. #include <usb.h>
  21. #include "core.h"
  22. #include "gadget.h"
  23. #include <reset.h>
  24. #include <clk.h>
  25. #include <power/regulator.h>
  26. #include <linux/bitfield.h>
  27. #include <linux/bitops.h>
  28. #include <linux/compat.h>
  29. #include <asm/arch/usb-gx.h>
  30. /* USB Glue Control Registers */
  31. #define USB_R0 0x00
  32. #define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
  33. #define USB_R0_P30_PHY_RESET BIT(6)
  34. #define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7)
  35. #define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8)
  36. #define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9)
  37. #define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14)
  38. #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
  39. #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
  40. #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
  41. #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
  42. #define USB_R0_U2D_ACT BIT(31)
  43. #define USB_R1 0x04
  44. #define USB_R1_U3H_BIGENDIAN_GS BIT(0)
  45. #define USB_R1_U3H_PME_ENABLE BIT(1)
  46. #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2)
  47. #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7)
  48. #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12)
  49. #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
  50. #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
  51. #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
  52. #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
  53. #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
  54. #define USB_R2 0x08
  55. #define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0)
  56. #define USB_R2_P30_CR_READ BIT(16)
  57. #define USB_R2_P30_CR_WRITE BIT(17)
  58. #define USB_R2_P30_CR_CAP_ADDR BIT(18)
  59. #define USB_R2_P30_CR_CAP_DATA BIT(19)
  60. #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
  61. #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
  62. #define USB_R3 0x0c
  63. #define USB_R3_P30_SSC_ENABLE BIT(0)
  64. #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
  65. #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
  66. #define USB_R3_P30_REF_SSP_EN BIT(13)
  67. #define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16)
  68. #define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19)
  69. #define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24)
  70. #define USB_R4 0x10
  71. #define USB_R4_P21_PORT_RESET_0 BIT(0)
  72. #define USB_R4_P21_SLEEP_M0 BIT(1)
  73. #define USB_R4_MEM_PD_MASK GENMASK(3, 2)
  74. #define USB_R4_P21_ONLY BIT(4)
  75. #define USB_R5 0x14
  76. #define USB_R5_ID_DIG_SYNC BIT(0)
  77. #define USB_R5_ID_DIG_REG BIT(1)
  78. #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
  79. #define USB_R5_ID_DIG_EN_0 BIT(4)
  80. #define USB_R5_ID_DIG_EN_1 BIT(5)
  81. #define USB_R5_ID_DIG_CURR BIT(6)
  82. #define USB_R5_ID_DIG_IRQ BIT(7)
  83. #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
  84. #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
  85. /* read-only register */
  86. #define USB_R6 0x18
  87. #define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0)
  88. #define USB_R6_P30_CR_ACK BIT(16)
  89. enum {
  90. USB2_HOST_PHY0 = 0,
  91. USB2_OTG_PHY1,
  92. USB2_HOST_PHY2,
  93. PHY_COUNT,
  94. };
  95. static const char *phy_names[PHY_COUNT] = {
  96. "usb2-phy0", "usb2-phy1", "usb2-phy2",
  97. };
  98. struct dwc3_meson_gxl {
  99. struct udevice *dev;
  100. struct regmap *regmap;
  101. struct clk clk;
  102. struct reset_ctl reset;
  103. struct phy phys[PHY_COUNT];
  104. enum usb_dr_mode otg_mode;
  105. enum usb_dr_mode otg_phy_mode;
  106. unsigned int usb2_ports;
  107. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  108. struct udevice *vbus_supply;
  109. #endif
  110. };
  111. #define U2P_REG_SIZE 0x20
  112. #define USB_REG_OFFSET 0x80
  113. #define USB2_OTG_PHY USB2_OTG_PHY1
  114. static void dwc3_meson_gxl_usb2_set_mode(struct dwc3_meson_gxl *priv, enum usb_dr_mode mode)
  115. {
  116. switch (mode) {
  117. case USB_DR_MODE_HOST:
  118. case USB_DR_MODE_OTG:
  119. case USB_DR_MODE_UNKNOWN:
  120. regmap_update_bits(priv->regmap, USB_R1,
  121. USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK, 0);
  122. regmap_update_bits(priv->regmap, USB_R0,
  123. USB_R0_U2D_ACT, 0);
  124. regmap_update_bits(priv->regmap, USB_R4,
  125. USB_R4_P21_SLEEP_M0, 0);
  126. break;
  127. case USB_DR_MODE_PERIPHERAL:
  128. regmap_update_bits(priv->regmap, USB_R0,
  129. USB_R0_U2D_ACT, USB_R0_U2D_ACT);
  130. regmap_update_bits(priv->regmap, USB_R0,
  131. USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0);
  132. regmap_update_bits(priv->regmap, USB_R4,
  133. USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
  134. break;
  135. }
  136. }
  137. static int dwc3_meson_gxl_usb2_init(struct dwc3_meson_gxl *priv)
  138. {
  139. int i;
  140. for (i = 0; i < PHY_COUNT; ++i) {
  141. if (!priv->phys[i].dev)
  142. continue;
  143. phy_meson_gxl_usb2_set_mode(&priv->phys[i],
  144. (i == USB2_OTG_PHY) ? USB_DR_MODE_PERIPHERAL
  145. : USB_DR_MODE_HOST);
  146. }
  147. return 0;
  148. }
  149. static int dwc3_meson_gxl_usb_init(struct dwc3_meson_gxl *priv)
  150. {
  151. int ret;
  152. ret = dwc3_meson_gxl_usb2_init(priv);
  153. if (ret)
  154. return ret;
  155. regmap_update_bits(priv->regmap, USB_R1,
  156. USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
  157. FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));
  158. regmap_update_bits(priv->regmap, USB_R5,
  159. USB_R5_ID_DIG_EN_0,
  160. USB_R5_ID_DIG_EN_0);
  161. regmap_update_bits(priv->regmap, USB_R5,
  162. USB_R5_ID_DIG_EN_1,
  163. USB_R5_ID_DIG_EN_1);
  164. regmap_update_bits(priv->regmap, USB_R5,
  165. USB_R5_ID_DIG_TH_MASK,
  166. FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));
  167. dwc3_meson_gxl_usb2_set_mode(priv, priv->otg_phy_mode);
  168. return 0;
  169. }
  170. int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode)
  171. {
  172. struct dwc3_meson_gxl *priv = dev_get_platdata(dev);
  173. if (!priv)
  174. return -EINVAL;
  175. if (mode != USB_DR_MODE_HOST && mode != USB_DR_MODE_PERIPHERAL)
  176. return -EINVAL;
  177. if (!priv->phys[USB2_OTG_PHY].dev)
  178. return -EINVAL;
  179. if (mode == priv->otg_phy_mode)
  180. return 0;
  181. if (mode == USB_DR_MODE_HOST)
  182. debug("%s: switching to Host Mode\n", __func__);
  183. else
  184. debug("%s: switching to Device Mode\n", __func__);
  185. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  186. if (priv->vbus_supply) {
  187. int ret = regulator_set_enable(priv->vbus_supply,
  188. (mode == USB_DR_MODE_PERIPHERAL));
  189. if (ret)
  190. return ret;
  191. }
  192. #endif
  193. priv->otg_phy_mode = mode;
  194. phy_meson_gxl_usb2_set_mode(&priv->phys[USB2_OTG_PHY], mode);
  195. dwc3_meson_gxl_usb2_set_mode(priv, mode);
  196. return 0;
  197. }
  198. static int dwc3_meson_gxl_get_phys(struct dwc3_meson_gxl *priv)
  199. {
  200. int i, ret;
  201. for (i = 0 ; i < PHY_COUNT ; ++i) {
  202. ret = generic_phy_get_by_name(priv->dev, phy_names[i],
  203. &priv->phys[i]);
  204. if (ret == -ENOENT || ret == -ENODATA) {
  205. priv->phys[i].dev = NULL;
  206. continue;
  207. }
  208. if (ret)
  209. return ret;
  210. priv->usb2_ports++;
  211. }
  212. debug("%s: usb2 ports: %d\n", __func__, priv->usb2_ports);
  213. return 0;
  214. }
  215. static int dwc3_meson_gxl_reset_init(struct dwc3_meson_gxl *priv)
  216. {
  217. int ret;
  218. ret = reset_get_by_index(priv->dev, 0, &priv->reset);
  219. if (ret)
  220. return ret;
  221. ret = reset_assert(&priv->reset);
  222. udelay(1);
  223. ret |= reset_deassert(&priv->reset);
  224. if (ret) {
  225. reset_free(&priv->reset);
  226. return ret;
  227. }
  228. return 0;
  229. }
  230. static int dwc3_meson_gxl_clk_init(struct dwc3_meson_gxl *priv)
  231. {
  232. int ret;
  233. ret = clk_get_by_index(priv->dev, 0, &priv->clk);
  234. if (ret)
  235. return ret;
  236. #if CONFIG_IS_ENABLED(CLK)
  237. ret = clk_enable(&priv->clk);
  238. if (ret) {
  239. clk_free(&priv->clk);
  240. return ret;
  241. }
  242. #endif
  243. return 0;
  244. }
  245. static int dwc3_meson_gxl_probe(struct udevice *dev)
  246. {
  247. struct dwc3_meson_gxl *priv = dev_get_platdata(dev);
  248. int ret, i;
  249. priv->dev = dev;
  250. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  251. if (ret)
  252. return ret;
  253. ret = dwc3_meson_gxl_clk_init(priv);
  254. if (ret)
  255. return ret;
  256. ret = dwc3_meson_gxl_reset_init(priv);
  257. if (ret)
  258. return ret;
  259. ret = dwc3_meson_gxl_get_phys(priv);
  260. if (ret)
  261. return ret;
  262. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  263. ret = device_get_supply_regulator(dev, "vbus-supply",
  264. &priv->vbus_supply);
  265. if (ret && ret != -ENOENT) {
  266. pr_err("Failed to get PHY regulator\n");
  267. return ret;
  268. }
  269. if (priv->vbus_supply) {
  270. ret = regulator_set_enable(priv->vbus_supply, true);
  271. if (ret)
  272. return ret;
  273. }
  274. #endif
  275. /* On GXL PHY must be started in device mode for DWC2 init */
  276. priv->otg_mode = USB_DR_MODE_PERIPHERAL;
  277. ret = dwc3_meson_gxl_usb_init(priv);
  278. if (ret)
  279. return ret;
  280. priv->otg_mode = usb_get_dr_mode(dev->node);
  281. if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
  282. priv->otg_phy_mode = USB_DR_MODE_PERIPHERAL;
  283. else
  284. priv->otg_phy_mode = USB_DR_MODE_HOST;
  285. for (i = 0 ; i < PHY_COUNT ; ++i) {
  286. if (!priv->phys[i].dev)
  287. continue;
  288. ret = generic_phy_init(&priv->phys[i]);
  289. if (ret)
  290. goto err_phy_init;
  291. }
  292. for (i = 0; i < PHY_COUNT; ++i) {
  293. if (!priv->phys[i].dev)
  294. continue;
  295. ret = generic_phy_power_on(&priv->phys[i]);
  296. if (ret)
  297. goto err_phy_init;
  298. }
  299. if (priv->phys[USB2_OTG_PHY].dev)
  300. phy_meson_gxl_usb2_set_mode(&priv->phys[USB2_OTG_PHY],
  301. priv->otg_phy_mode);
  302. dwc3_meson_gxl_usb2_set_mode(priv, priv->otg_phy_mode);
  303. return 0;
  304. err_phy_init:
  305. for (i = 0 ; i < PHY_COUNT ; ++i) {
  306. if (!priv->phys[i].dev)
  307. continue;
  308. generic_phy_exit(&priv->phys[i]);
  309. }
  310. return ret;
  311. }
  312. static int dwc3_meson_gxl_remove(struct udevice *dev)
  313. {
  314. struct dwc3_meson_gxl *priv = dev_get_platdata(dev);
  315. int i;
  316. reset_release_all(&priv->reset, 1);
  317. clk_release_all(&priv->clk, 1);
  318. for (i = 0; i < PHY_COUNT; ++i) {
  319. if (!priv->phys[i].dev)
  320. continue;
  321. generic_phy_power_off(&priv->phys[i]);
  322. }
  323. for (i = 0 ; i < PHY_COUNT ; ++i) {
  324. if (!priv->phys[i].dev)
  325. continue;
  326. generic_phy_exit(&priv->phys[i]);
  327. }
  328. return dm_scan_fdt_dev(dev);
  329. }
  330. static const struct udevice_id dwc3_meson_gxl_ids[] = {
  331. { .compatible = "amlogic,meson-gxl-usb-ctrl" },
  332. { .compatible = "amlogic,meson-gxm-usb-ctrl" },
  333. { }
  334. };
  335. U_BOOT_DRIVER(dwc3_generic_wrapper) = {
  336. .name = "dwc3-meson-gxl",
  337. .id = UCLASS_SIMPLE_BUS,
  338. .of_match = dwc3_meson_gxl_ids,
  339. .probe = dwc3_meson_gxl_probe,
  340. .remove = dwc3_meson_gxl_remove,
  341. .platdata_auto_alloc_size = sizeof(struct dwc3_meson_gxl),
  342. };