dwc3-generic.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Generic DWC3 Glue layer
  4. *
  5. * Copyright (C) 2016 - 2018 Xilinx, Inc.
  6. *
  7. * Based on dwc3-omap.c.
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <log.h>
  12. #include <dm.h>
  13. #include <dm/device-internal.h>
  14. #include <dm/lists.h>
  15. #include <dwc3-uboot.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include <linux/usb/ch9.h>
  19. #include <linux/usb/gadget.h>
  20. #include <malloc.h>
  21. #include <usb.h>
  22. #include "core.h"
  23. #include "gadget.h"
  24. #include <reset.h>
  25. #include <clk.h>
  26. #include <usb/xhci.h>
  27. struct dwc3_glue_data {
  28. struct clk_bulk clks;
  29. struct reset_ctl_bulk resets;
  30. fdt_addr_t regs;
  31. };
  32. struct dwc3_generic_plat {
  33. fdt_addr_t base;
  34. u32 maximum_speed;
  35. enum usb_dr_mode dr_mode;
  36. };
  37. struct dwc3_generic_priv {
  38. void *base;
  39. struct dwc3 dwc3;
  40. struct phy_bulk phys;
  41. };
  42. struct dwc3_generic_host_priv {
  43. struct xhci_ctrl xhci_ctrl;
  44. struct dwc3_generic_priv gen_priv;
  45. };
  46. static int dwc3_generic_probe(struct udevice *dev,
  47. struct dwc3_generic_priv *priv)
  48. {
  49. int rc;
  50. struct dwc3_generic_plat *plat = dev_get_platdata(dev);
  51. struct dwc3 *dwc3 = &priv->dwc3;
  52. struct dwc3_glue_data *glue = dev_get_platdata(dev->parent);
  53. dwc3->dev = dev;
  54. dwc3->maximum_speed = plat->maximum_speed;
  55. dwc3->dr_mode = plat->dr_mode;
  56. #if CONFIG_IS_ENABLED(OF_CONTROL)
  57. dwc3_of_parse(dwc3);
  58. #endif
  59. /*
  60. * It must hold whole USB3.0 OTG controller in resetting to hold pipe
  61. * power state in P2 before initializing TypeC PHY on RK3399 platform.
  62. */
  63. if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
  64. reset_assert_bulk(&glue->resets);
  65. udelay(1);
  66. }
  67. rc = dwc3_setup_phy(dev, &priv->phys);
  68. if (rc)
  69. return rc;
  70. if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
  71. reset_deassert_bulk(&glue->resets);
  72. priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
  73. dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
  74. rc = dwc3_init(dwc3);
  75. if (rc) {
  76. unmap_physmem(priv->base, MAP_NOCACHE);
  77. return rc;
  78. }
  79. return 0;
  80. }
  81. static int dwc3_generic_remove(struct udevice *dev,
  82. struct dwc3_generic_priv *priv)
  83. {
  84. struct dwc3 *dwc3 = &priv->dwc3;
  85. dwc3_remove(dwc3);
  86. dwc3_shutdown_phy(dev, &priv->phys);
  87. unmap_physmem(dwc3->regs, MAP_NOCACHE);
  88. return 0;
  89. }
  90. static int dwc3_generic_ofdata_to_platdata(struct udevice *dev)
  91. {
  92. struct dwc3_generic_plat *plat = dev_get_platdata(dev);
  93. ofnode node = dev->node;
  94. plat->base = dev_read_addr(dev);
  95. plat->maximum_speed = usb_get_maximum_speed(node);
  96. if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
  97. pr_info("No USB maximum speed specified. Using super speed\n");
  98. plat->maximum_speed = USB_SPEED_SUPER;
  99. }
  100. plat->dr_mode = usb_get_dr_mode(node);
  101. if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
  102. pr_err("Invalid usb mode setup\n");
  103. return -ENODEV;
  104. }
  105. return 0;
  106. }
  107. #if CONFIG_IS_ENABLED(DM_USB_GADGET)
  108. int dm_usb_gadget_handle_interrupts(struct udevice *dev)
  109. {
  110. struct dwc3_generic_priv *priv = dev_get_priv(dev);
  111. struct dwc3 *dwc3 = &priv->dwc3;
  112. dwc3_gadget_uboot_handle_interrupt(dwc3);
  113. return 0;
  114. }
  115. static int dwc3_generic_peripheral_probe(struct udevice *dev)
  116. {
  117. struct dwc3_generic_priv *priv = dev_get_priv(dev);
  118. return dwc3_generic_probe(dev, priv);
  119. }
  120. static int dwc3_generic_peripheral_remove(struct udevice *dev)
  121. {
  122. struct dwc3_generic_priv *priv = dev_get_priv(dev);
  123. return dwc3_generic_remove(dev, priv);
  124. }
  125. U_BOOT_DRIVER(dwc3_generic_peripheral) = {
  126. .name = "dwc3-generic-peripheral",
  127. .id = UCLASS_USB_GADGET_GENERIC,
  128. .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
  129. .probe = dwc3_generic_peripheral_probe,
  130. .remove = dwc3_generic_peripheral_remove,
  131. .priv_auto_alloc_size = sizeof(struct dwc3_generic_priv),
  132. .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
  133. };
  134. #endif
  135. #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
  136. static int dwc3_generic_host_probe(struct udevice *dev)
  137. {
  138. struct xhci_hcor *hcor;
  139. struct xhci_hccr *hccr;
  140. struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
  141. int rc;
  142. rc = dwc3_generic_probe(dev, &priv->gen_priv);
  143. if (rc)
  144. return rc;
  145. hccr = (struct xhci_hccr *)priv->gen_priv.base;
  146. hcor = (struct xhci_hcor *)(priv->gen_priv.base +
  147. HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
  148. return xhci_register(dev, hccr, hcor);
  149. }
  150. static int dwc3_generic_host_remove(struct udevice *dev)
  151. {
  152. struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
  153. int rc;
  154. rc = xhci_deregister(dev);
  155. if (rc)
  156. return rc;
  157. return dwc3_generic_remove(dev, &priv->gen_priv);
  158. }
  159. U_BOOT_DRIVER(dwc3_generic_host) = {
  160. .name = "dwc3-generic-host",
  161. .id = UCLASS_USB,
  162. .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
  163. .probe = dwc3_generic_host_probe,
  164. .remove = dwc3_generic_host_remove,
  165. .priv_auto_alloc_size = sizeof(struct dwc3_generic_host_priv),
  166. .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
  167. .ops = &xhci_usb_ops,
  168. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  169. };
  170. #endif
  171. struct dwc3_glue_ops {
  172. void (*select_dr_mode)(struct udevice *dev, int index,
  173. enum usb_dr_mode mode);
  174. };
  175. void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
  176. enum usb_dr_mode mode)
  177. {
  178. #define USBOTGSS_UTMI_OTG_STATUS 0x0084
  179. #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
  180. /* UTMI_OTG_STATUS REGISTER */
  181. #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE BIT(31)
  182. #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT BIT(9)
  183. #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
  184. #define USBOTGSS_UTMI_OTG_STATUS_IDDIG BIT(4)
  185. #define USBOTGSS_UTMI_OTG_STATUS_SESSEND BIT(3)
  186. #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID BIT(2)
  187. #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID BIT(1)
  188. enum dwc3_omap_utmi_mode {
  189. DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
  190. DWC3_OMAP_UTMI_MODE_HW,
  191. DWC3_OMAP_UTMI_MODE_SW,
  192. };
  193. u32 use_id_pin;
  194. u32 host_mode;
  195. u32 reg;
  196. u32 utmi_mode;
  197. u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
  198. struct dwc3_glue_data *glue = dev_get_platdata(dev);
  199. void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
  200. if (device_is_compatible(dev, "ti,am437x-dwc3"))
  201. utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;
  202. utmi_mode = dev_read_u32_default(dev, "utmi-mode",
  203. DWC3_OMAP_UTMI_MODE_UNKNOWN);
  204. if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
  205. debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
  206. dev->name);
  207. mode = USB_DR_MODE_PERIPHERAL;
  208. }
  209. switch (mode) {
  210. case USB_DR_MODE_PERIPHERAL:
  211. use_id_pin = 0;
  212. host_mode = 0;
  213. break;
  214. case USB_DR_MODE_HOST:
  215. use_id_pin = 0;
  216. host_mode = 1;
  217. break;
  218. case USB_DR_MODE_OTG:
  219. default:
  220. use_id_pin = 1;
  221. host_mode = 0;
  222. break;
  223. }
  224. reg = readl(base + utmi_status_offset);
  225. reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
  226. if (!use_id_pin)
  227. reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
  228. writel(reg, base + utmi_status_offset);
  229. reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND |
  230. USBOTGSS_UTMI_OTG_STATUS_VBUSVALID |
  231. USBOTGSS_UTMI_OTG_STATUS_IDDIG);
  232. reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID |
  233. USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
  234. if (!host_mode)
  235. reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG |
  236. USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;
  237. writel(reg, base + utmi_status_offset);
  238. unmap_physmem(base, MAP_NOCACHE);
  239. }
  240. struct dwc3_glue_ops ti_ops = {
  241. .select_dr_mode = dwc3_ti_select_dr_mode,
  242. };
  243. static int dwc3_glue_bind(struct udevice *parent)
  244. {
  245. ofnode node;
  246. int ret;
  247. ofnode_for_each_subnode(node, parent->node) {
  248. const char *name = ofnode_get_name(node);
  249. enum usb_dr_mode dr_mode;
  250. struct udevice *dev;
  251. const char *driver = NULL;
  252. debug("%s: subnode name: %s\n", __func__, name);
  253. dr_mode = usb_get_dr_mode(node);
  254. switch (dr_mode) {
  255. case USB_DR_MODE_PERIPHERAL:
  256. case USB_DR_MODE_OTG:
  257. #if CONFIG_IS_ENABLED(DM_USB_GADGET)
  258. debug("%s: dr_mode: OTG or Peripheral\n", __func__);
  259. driver = "dwc3-generic-peripheral";
  260. #endif
  261. break;
  262. #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
  263. case USB_DR_MODE_HOST:
  264. debug("%s: dr_mode: HOST\n", __func__);
  265. driver = "dwc3-generic-host";
  266. break;
  267. #endif
  268. default:
  269. debug("%s: unsupported dr_mode\n", __func__);
  270. return -ENODEV;
  271. };
  272. if (!driver)
  273. continue;
  274. ret = device_bind_driver_to_node(parent, driver, name,
  275. node, &dev);
  276. if (ret) {
  277. debug("%s: not able to bind usb device mode\n",
  278. __func__);
  279. return ret;
  280. }
  281. }
  282. return 0;
  283. }
  284. static int dwc3_glue_reset_init(struct udevice *dev,
  285. struct dwc3_glue_data *glue)
  286. {
  287. int ret;
  288. ret = reset_get_bulk(dev, &glue->resets);
  289. if (ret == -ENOTSUPP || ret == -ENOENT)
  290. return 0;
  291. else if (ret)
  292. return ret;
  293. ret = reset_deassert_bulk(&glue->resets);
  294. if (ret) {
  295. reset_release_bulk(&glue->resets);
  296. return ret;
  297. }
  298. return 0;
  299. }
  300. static int dwc3_glue_clk_init(struct udevice *dev,
  301. struct dwc3_glue_data *glue)
  302. {
  303. int ret;
  304. ret = clk_get_bulk(dev, &glue->clks);
  305. if (ret == -ENOSYS || ret == -ENOENT)
  306. return 0;
  307. if (ret)
  308. return ret;
  309. #if CONFIG_IS_ENABLED(CLK)
  310. ret = clk_enable_bulk(&glue->clks);
  311. if (ret) {
  312. clk_release_bulk(&glue->clks);
  313. return ret;
  314. }
  315. #endif
  316. return 0;
  317. }
  318. static int dwc3_glue_probe(struct udevice *dev)
  319. {
  320. struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev);
  321. struct dwc3_glue_data *glue = dev_get_platdata(dev);
  322. struct udevice *child = NULL;
  323. int index = 0;
  324. int ret;
  325. glue->regs = dev_read_addr(dev);
  326. ret = dwc3_glue_clk_init(dev, glue);
  327. if (ret)
  328. return ret;
  329. ret = dwc3_glue_reset_init(dev, glue);
  330. if (ret)
  331. return ret;
  332. ret = device_find_first_child(dev, &child);
  333. if (ret)
  334. return ret;
  335. if (glue->resets.count == 0) {
  336. ret = dwc3_glue_reset_init(child, glue);
  337. if (ret)
  338. return ret;
  339. }
  340. while (child) {
  341. enum usb_dr_mode dr_mode;
  342. dr_mode = usb_get_dr_mode(child->node);
  343. device_find_next_child(&child);
  344. if (ops && ops->select_dr_mode)
  345. ops->select_dr_mode(dev, index, dr_mode);
  346. index++;
  347. }
  348. return 0;
  349. }
  350. static int dwc3_glue_remove(struct udevice *dev)
  351. {
  352. struct dwc3_glue_data *glue = dev_get_platdata(dev);
  353. reset_release_bulk(&glue->resets);
  354. clk_release_bulk(&glue->clks);
  355. return 0;
  356. }
  357. static const struct udevice_id dwc3_glue_ids[] = {
  358. { .compatible = "xlnx,zynqmp-dwc3" },
  359. { .compatible = "xlnx,versal-dwc3" },
  360. { .compatible = "ti,keystone-dwc3"},
  361. { .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
  362. { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
  363. { .compatible = "ti,am654-dwc3" },
  364. { .compatible = "rockchip,rk3328-dwc3" },
  365. { .compatible = "rockchip,rk3399-dwc3" },
  366. { .compatible = "qcom,dwc3" },
  367. { }
  368. };
  369. U_BOOT_DRIVER(dwc3_generic_wrapper) = {
  370. .name = "dwc3-generic-wrapper",
  371. .id = UCLASS_NOP,
  372. .of_match = dwc3_glue_ids,
  373. .bind = dwc3_glue_bind,
  374. .probe = dwc3_glue_probe,
  375. .remove = dwc3_glue_remove,
  376. .platdata_auto_alloc_size = sizeof(struct dwc3_glue_data),
  377. };