board-axg.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch/boot.h>
  10. #include <asm/arch/eth.h>
  11. #include <asm/arch/axg.h>
  12. #include <asm/arch/mem.h>
  13. #include <asm/io.h>
  14. #include <asm/armv8/mmu.h>
  15. #include <linux/sizes.h>
  16. #include <usb.h>
  17. #include <linux/usb/otg.h>
  18. #include <asm/arch/usb-gx.h>
  19. #include <usb/dwc2_udc.h>
  20. #include <clk.h>
  21. #include <phy.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. int meson_get_boot_device(void)
  24. {
  25. return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
  26. }
  27. /* Configure the reserved memory zones exported by the secure registers
  28. * into EFI and DTB reserved memory entries.
  29. */
  30. void meson_init_reserved_memory(void *fdt)
  31. {
  32. u64 bl31_size, bl31_start;
  33. u64 bl32_size, bl32_start;
  34. u32 reg;
  35. /*
  36. * Get ARM Trusted Firmware reserved memory zones in :
  37. * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  38. * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  39. * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  40. */
  41. reg = readl(AXG_AO_SEC_GP_CFG3);
  42. bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
  43. >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  44. bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  45. bl31_start = readl(AXG_AO_SEC_GP_CFG5);
  46. bl32_start = readl(AXG_AO_SEC_GP_CFG4);
  47. /* Add BL31 reserved zone */
  48. if (bl31_start && bl31_size)
  49. meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  50. /* Add BL32 reserved zone */
  51. if (bl32_start && bl32_size)
  52. meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  53. }
  54. phys_size_t get_effective_memsize(void)
  55. {
  56. /* Size is reported in MiB, convert it in bytes */
  57. return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
  58. >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
  59. }
  60. static struct mm_region axg_mem_map[] = {
  61. {
  62. .virt = 0x0UL,
  63. .phys = 0x0UL,
  64. .size = 0x80000000UL,
  65. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  66. PTE_BLOCK_INNER_SHARE
  67. }, {
  68. .virt = 0xf0000000UL,
  69. .phys = 0xf0000000UL,
  70. .size = 0x10000000UL,
  71. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  72. PTE_BLOCK_NON_SHARE |
  73. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  74. }, {
  75. /* List terminator */
  76. 0,
  77. }
  78. };
  79. struct mm_region *mem_map = axg_mem_map;
  80. /* Configure the Ethernet MAC with the requested interface mode
  81. * with some optional flags.
  82. */
  83. void meson_eth_init(phy_interface_t mode, unsigned int flags)
  84. {
  85. switch (mode) {
  86. case PHY_INTERFACE_MODE_RGMII:
  87. case PHY_INTERFACE_MODE_RGMII_ID:
  88. case PHY_INTERFACE_MODE_RGMII_RXID:
  89. case PHY_INTERFACE_MODE_RGMII_TXID:
  90. /* Set RGMII mode */
  91. setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
  92. AXG_ETH_REG_0_TX_PHASE(1) |
  93. AXG_ETH_REG_0_TX_RATIO(4) |
  94. AXG_ETH_REG_0_PHY_CLK_EN |
  95. AXG_ETH_REG_0_CLK_EN);
  96. break;
  97. case PHY_INTERFACE_MODE_RMII:
  98. /* Set RMII mode */
  99. out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
  100. AXG_ETH_REG_0_INVERT_RMII_CLK |
  101. AXG_ETH_REG_0_CLK_EN);
  102. break;
  103. default:
  104. printf("Invalid Ethernet interface mode\n");
  105. return;
  106. }
  107. /* Enable power gate */
  108. clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
  109. }
  110. #if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
  111. CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
  112. static struct dwc2_plat_otg_data meson_gx_dwc2_data;
  113. int board_usb_init(int index, enum usb_init_type init)
  114. {
  115. struct fdtdec_phandle_args args;
  116. const void *blob = gd->fdt_blob;
  117. int node, dwc2_node;
  118. struct udevice *dev, *clk_dev;
  119. struct clk clk;
  120. int ret;
  121. /* find the usb glue node */
  122. node = fdt_node_offset_by_compatible(blob, -1,
  123. "amlogic,meson-gxl-usb-ctrl");
  124. if (node < 0) {
  125. debug("Not found usb-control node\n");
  126. return -ENODEV;
  127. }
  128. if (!fdtdec_get_is_enabled(blob, node)) {
  129. debug("usb is disabled in the device tree\n");
  130. return -ENODEV;
  131. }
  132. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  133. if (ret) {
  134. debug("Not found usb-control device\n");
  135. return ret;
  136. }
  137. /* find the dwc2 node */
  138. dwc2_node = fdt_node_offset_by_compatible(blob, node,
  139. "amlogic,meson-g12a-usb");
  140. if (dwc2_node < 0) {
  141. debug("Not found dwc2 node\n");
  142. return -ENODEV;
  143. }
  144. if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
  145. debug("dwc2 is disabled in the device tree\n");
  146. return -ENODEV;
  147. }
  148. meson_gx_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
  149. if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
  150. debug("usbotg: can't get base address\n");
  151. return -ENODATA;
  152. }
  153. /* Enable clock */
  154. ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
  155. "#clock-cells", 0, 0, &args);
  156. if (ret) {
  157. debug("usbotg has no clocks defined in the device tree\n");
  158. return ret;
  159. }
  160. ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
  161. if (ret)
  162. return ret;
  163. if (args.args_count != 1) {
  164. debug("Can't find clock ID in the device tree\n");
  165. return -ENODATA;
  166. }
  167. clk.dev = clk_dev;
  168. clk.id = args.args[0];
  169. ret = clk_enable(&clk);
  170. if (ret) {
  171. debug("Failed to enable usbotg clock\n");
  172. return ret;
  173. }
  174. meson_gx_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  175. "g-rx-fifo-size", 0);
  176. meson_gx_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  177. "g-np-tx-fifo-size", 0);
  178. meson_gx_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  179. "g-tx-fifo-size", 0);
  180. /* Switch to peripheral mode */
  181. ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_PERIPHERAL);
  182. if (ret)
  183. return ret;
  184. return dwc2_udc_probe(&meson_gx_dwc2_data);
  185. }
  186. int board_usb_cleanup(int index, enum usb_init_type init)
  187. {
  188. const void *blob = gd->fdt_blob;
  189. struct udevice *dev;
  190. int node;
  191. int ret;
  192. /* find the usb glue node */
  193. node = fdt_node_offset_by_compatible(blob, -1,
  194. "amlogic,meson-gxl-usb-ctrl");
  195. if (node < 0) {
  196. debug("Not found usb-control node\n");
  197. return -ENODEV;
  198. }
  199. if (!fdtdec_get_is_enabled(blob, node))
  200. return -ENODEV;
  201. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  202. if (ret)
  203. return ret;
  204. /* Switch to OTG mode */
  205. ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_HOST);
  206. if (ret)
  207. return ret;
  208. return 0;
  209. }
  210. #endif